A 14ns 256kx1 CMOS SRAM with multiple test modes

Abstract

The memory organization is partitioned into four 64k matrices. The power to the submicron CMOS memory cells is supplied by an on-chip switching voltage regulator. The 3.9V matrix supply protects the memory cells against hot carrier stress and ensures high cell noise margins'. In the 5V periphery, 1 . 3 ~ NMOS cascode devices were integrated'. Each matrix is organized in 128 rows by 512 columns and is further divided into 16 blocks of 32 columns, utilizing a divided word line structure3. A common read/write block area with local sense amplifiers and write drivers is shared between each pair of matrices. A matrix global Y-select signal enables one of eight columns and precharges the remaining unselected columns to the matrix voltage (VDI).