8ns 64K BiCMOS SRAM's

INTRODUCTION S ince Bi-CMOS technology employs h ighd r i v a b i l i t y g a t e c i r c u i t s and h i g h s e n s i t i v i t y Sense c i r c u i t s , h i g h e r speed memory c i r c u i t s than t h o s e through CMOS p r o c e s s technology can b e ach ieved . This paper d e s c r i b e s 64K TTL SRAM d e s i g n us ing 1 . 3 u m Hi-BiCMOS technology. A 16Kw x 4b o r 64Kw x Ib RAM i s c o n f i g u r a b l e by changing t h e w i r i n g l a y e r c o n f i g u r a t i o n . I n t h i s R A M , t he c u r r e n t source c i r c u i t i s s t a b i l i z e d a g a i n s t power-supply v o l t a g e Vcc and t empera tu re so t h a t i n c r e a s e i n a c c e s s t ime a s we l l a s i n power consumption under t h e wors t c o n d i t i o n s a r e minimized. The a d d r e s s a c c e s s time of t h e RAM i s 8 .0 ns and t h e a c t i v e c u r r e n t i s 45 mA under the c o n d i t i o n s of Vcc=5.0 V , Ta=25"C, and 50 M H r .