T. Morita, T. Hayashi, Y. Saita, T. Ohno, S. Yoshida, T. Fukuda, R. Ikeda
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A 5.5 MIPS call handling processor for switching systems
A 3 2 b i t P r o c a s s o r f o r ESS ( E l e c t r o n i c S w i t c h l n s S y s t e m s ) w i t h m i x e d (R ISC & C iSC) i n s t r u c t i o n s e t i s d e s c r i b e d . The p e r f o r m a n c e i s a c h i e v e d by a 4 s t a g e P i p e l i n e and t h e l o c a l s t o r a g e f o r R i S C l i k e i n s t r u c t i o n s and b y WCS ( W r i t a b l e C o n t r o l S t o r a g e ) f o r C iSC l i k e i n s t r u c t i o n s a t 16MHz. U s i n s 1 . 2 m i c r o n d o u b l e m e t a l CMOS t s c h n a l o o v . t h e c h i p c o n t a i n s 160K t r a n s i s t o r s o n a 13.2x13.7 mm d i e .
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