A circuit design of 32Kbyte integrated cache memory

Abstract

Introduction A w h e memory is effective in enhancing CPU system throughput[lI. A circuit design aspect of a newly developed integrated cache memory which includes 32Kbyte DATA memory, with a typical IUT delay of 18ns is desnibed. The present memory achieves four times larger DATA memory size together with much faster operation sped compared with the recenlly reponed integrated cache memory[2l. The memory includes 32Kbyte DATA (INSISTRUCTION) memory, 3Kbit TAG memory. XKbit VALID flag, 2Kbit LRU flag. comparator. and CPU interface logic circuits. The inclusion of DATA memory is imponant in improving system cycle time as shown in Fig.1. It is also imponant for reducing board area and cost, because it replaces about ten LSl's.