A novel BiCMOS TTL input buffer; a merging of analog and digital circuit design techniques

1 TIL ML The advent of BiCMOS technology brings the availability of bipolar and CMOS components to one silicon chip, and allows the integration oi bipolar high preeirion analog circuita with lower power digital circuitry in next generation of high performance products [l]. This paper will describe a BiCMOS TTL input buffer which employs analog circuit design techniques to enhance the circuit performance. This novel implementation demonstrates the broad range of analog design techniques which can be applied in BiCMOS digital c k u i t s . The Mynchronoua operation CMOS TTL input buffer has two major obstacles that have been taunting IC circuit designers-for years. First is the variations of input trip point across power .up ply, process and temperature. Second is the high power dissipation of the buffer's first stage inverter, which results from the small voltage swing of the TTL input level. Furthermore, for eompatibility to the standby power requirements of the existing products, a CMOS input buffer often must be gated by an enabling signal for switching lo and from the standby mode. These problems require compromises to be made between speed, power, yield and reliability. and thus tend to degrade the overall performance oi the device. The transistor i i a e s of the buffer's fint stsge inverter are chosen surh that the DC trip point is centered et a midpoint of the TTL input level (1.4 volts). However, as process, power supply and temperature fluctuate. the DC trip point deviates away from the midpoint and reduces the input signal margins, as shown in figure 1. In additional, a significant current is Bowing in the CMOS input buffer when its input 1s at TTL VIH level of 2.0 volts, M shown in figure 2a. This current is caused by the CMOS input buffer's first stage inverter which is partially in an on state. reference voltage of 1.4 volts LO II Threshold Reference (TREF) ckcuit to establish a CMOS inverter trip point dependent VTH signal. This signal is connected to bipolar transistor Q1 to supply a rcgulated voltage level to the source of the Pchannel pull-up MP1. This voltage level is designed to keep the trip point of the TCON input buffer's h t stage inverter at the midpoint of TTL high and low levels. The transistor sizes of the first stage inverter M also chosen such that the voltage a t the source ofthe Pchannel MPI ir alwayat or below L voltage level of (VTTLhi + Vtp); where VTTLhi is the TTL logic high level of 2.0 volts and Vtp is the Vt of the Pchanne1 transistor. Figure 2b shows a plot of the current of the TCON input buffer vs its input voltage when condition stated above is satisfied. The buffer (current is essentially ~ e r o when its input is held at a valid TTL level. This important feature allows the standby to active enabling signal to he omitted from the design of the input circuitry. The elimination of this enabling signal allows faster eircui1 operation because the output of the buffer is in II correct logic state during the standby period.