具有ECL接口的6.2 ns 64Kb CMOS RAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI:10.1109/VLSIC.1988.1037404

T. Chappell, S. Schuster, B. Chappell, J. Allan, S. Klepner, R. Franch, P. Greier, P. Restle

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引用次数: 10

摘要

INTQnnl lrTlnN y地址。Dolo-In。和写控制例(22例)。这些在.. .. ..----. .-.. .. ..pts使用图2所示的动态检测放大器接收器，具有慢置和快置时钟，用于ecl到cmos转换。与dram一样，动态检测放大器在小至100 mV的信号下可靠地工作。虽然这个接收器比x地址接收器慢一些。它没有直流待机DOWCT，并且在双极和BiCMOS技术中仍然报道了许多具有ECL接口的Sub-lo - 64Kb sram [I-21]。本文报道了第一个具有ECL接口信号的10ns以下64Kb CMOS RAM。这种RAM的高性能是由于创新的结合。并采用先进的CMOS电路设计。采用0.5 pm Leff的SeleCti”elY缩放CMOS工艺，这两者都将被描述。

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A 6.2 ns 64Kb CMOS RAM with ECL interfaces

INTQnnl lrTlnN Y-Address. Dolo-In. and Write Conrrol Inouls (22 Inoulsl. These in.. . . ..----. .-.. . . . . pnts use the dynamic sense amplifier receiver shown in Fig. 2 with slow-set and fast-set clocking for ECL-to-CMOS conversion. As in DRAMS, the dynamic sense amplifier operates reliably with signals as small as 100 mV. Although this receiver is somewhat slower than the X-address receiver. it has no DC standby DOWCT and it is still much Sub-lo ns 64Kb SRAMs with ECL interfaces have been reported in both bipolar and BiCMOS technologies [I-21. This Paper reports the first sub-10 ns 64Kb CMOS RAM with ECL interface signals. The high performance of this RAM is due to the combination of innova_ . tive CMOS circuit design and an advanced. SeleCti"elY scaled CMOS process with 0.5 pm Leff, both of which will be described.

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Symposium 1988 on VLSI Circuits

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