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Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems最新文献

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Tools for validating asynchronous digital circuits 验证异步数字电路的工具
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656282
A. Ashkinazy, D. A. Edwards, C. Farnsworth, Gary Gendel, Shiv S. Sikand
{"title":"Tools for validating asynchronous digital circuits","authors":"A. Ashkinazy, D. A. Edwards, C. Farnsworth, Gary Gendel, Shiv S. Sikand","doi":"10.1109/ASYNC.1994.656282","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656282","url":null,"abstract":"Asynchronous design methodologies can yield designs that are smaller and/or consume less power, than their synchronous counterparts. Traditional tools, oriented toward synchronous designs, may miss critical asynchronous design problems. This paper describes the modeling methodology and hazard analysis of the SlMIC logic simulator that address asynchronous designs. It also describes tools and a methodology for generating accurate timing models from SPICE simulations and for analyzing and viewing dynamic power consumption. Finally, it presents a case study illustrating the use of these tools in a leading-edge asynchronous design.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Sufficient conditions for correct gate-level speed-independent circuits 正确的门级速度无关电路的充分条件
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656284
P. Beerel, J. Burch, T. Meng
{"title":"Sufficient conditions for correct gate-level speed-independent circuits","authors":"P. Beerel, J. Burch, T. Meng","doi":"10.1109/ASYNC.1994.656284","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656284","url":null,"abstract":"We describe sufficient conditions for the correctness of speed-independent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of single-output basic gates. A circuit is defined to be correct if it is hazard-free and complex-gate equivalent to its specification. We show that a circuit is hazard-free if and only if all of its signals are monotonic and acknowledged. This result provides a useful tool for formal reasoning about the correctness of circuits and synthesis techniques. Cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are the basis of efficient synthesis and verification algorithms.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"6 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120891701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Building fast bundled data circuits with a specialized standard cell library 用专门的标准单元库构建快速捆绑数据电路
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656302
P. T. Røine
{"title":"Building fast bundled data circuits with a specialized standard cell library","authors":"P. T. Røine","doi":"10.1109/ASYNC.1994.656302","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656302","url":null,"abstract":"A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 /spl mu/m CMOS process, achieves a throughput of about 150 million symbols per second.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133371390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Utilising dynamic logic for low power consumption in asynchronous circuits 在异步电路中利用动态逻辑实现低功耗
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656311
C. Farnsworth, D. A. Edwards, Shiv S. Sikand
{"title":"Utilising dynamic logic for low power consumption in asynchronous circuits","authors":"C. Farnsworth, D. A. Edwards, Shiv S. Sikand","doi":"10.1109/ASYNC.1994.656311","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656311","url":null,"abstract":"Dynamic logic offers compact, fast solutions for synchronous design. Asynchronous design methodologies which conform to the bounded-delay model can also utilise dynamic logic for combinational circuits obtaining similar benefits to the synchronous case. To achieve these benefits, the logic is held in precharge until it is required and the evaluation phase is completed during a handshake communication action. The resultant power consumption is low since the input capacitance is far smaller than equivalent static CMOS circuits and spurious transitions in the computation are removed.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Composable specifications for asynchronous systems using UNITY 使用UNITY的异步系统的可组合规范
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656314
M. Bickford
{"title":"Composable specifications for asynchronous systems using UNITY","authors":"M. Bickford","doi":"10.1109/ASYNC.1994.656314","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656314","url":null,"abstract":"Using UNITY as a model for asynchronous hardware systems, we give a generic specification of a device that obeys a four phase protocol. The specification is general enough to allow devices with bundled data as well as dual-rail coded ports, and two phase signalling can be seen as a special case. We give a generic implementation of a function cell and show that A. Martin's Adder cell is an instance. Finally, we prove two composition theorems that allow four phase devices to be combined into larger four phase devices. All stated theorems were checked using a mechanical theorem prover and we give complete definitions for all the concepts used in the generic specification.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Timing-reliability evaluation of asynchronous circuits based on different delay models 基于不同延迟模型的异步电路时序可靠性评估
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656283
M. Kuwako, T. Nanya
{"title":"Timing-reliability evaluation of asynchronous circuits based on different delay models","authors":"M. Kuwako, T. Nanya","doi":"10.1109/ASYNC.1994.656283","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656283","url":null,"abstract":"We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121448443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Designing asynchronous circuits from behavioural specifications with internal conflicts 从带有内部冲突的行为规范设计异步电路
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656296
J. Cortadella, L. Lavagno, P. Vanbekbergen, A. Yakovlev
{"title":"Designing asynchronous circuits from behavioural specifications with internal conflicts","authors":"J. Cortadella, L. Lavagno, P. Vanbekbergen, A. Yakovlev","doi":"10.1109/ASYNC.1994.656296","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656296","url":null,"abstract":"The paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the Petri net level, which introduce auxiliary signal transitions implemented by internally analogue components, Mutual Exclusion (ME) elements. The logic for primary outputs can therefore be realized free from hazards and external meta-stability. The technique draws upon the use of standard logic components and two-input MEs, available in a typical design library.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Partial scan test for asynchronous circuits illustrated on a DCC error corrector 异步电路的部分扫描测试，图示在DCC错误校正器上
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656318
M. Roncken
{"title":"Partial scan test for asynchronous circuits illustrated on a DCC error corrector","authors":"M. Roncken","doi":"10.1109/ASYNC.1994.656318","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656318","url":null,"abstract":"We present a design-for-testability method for asynchronous circuits based on partial scan. More specifically, we investigate how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and we show that asynchronous partial scan design can be approached as a high-level design activity. The method is demonstrated on an asynchronous error corrector for the DCC player. It has been used effectually in the production and application-mode tests of this 155 k transistor chip-set. In particular, it has led to high 99.9% stuck-at output fault coverage in short 64 msec test time at the expense of less than 3% additional area.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123541402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Characterizing speed-independence of high-level designs 描述高级设计的速度无关性
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656285
M. Kishinevsky, J. Staunstrup
{"title":"Characterizing speed-independence of high-level designs","authors":"M. Kishinevsky, J. Staunstrup","doi":"10.1109/ASYNC.1994.656285","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656285","url":null,"abstract":"This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent RAM, a complex switch of a data path, various Muller C-elements, FIFO registers, and counters.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127965511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra 异步DSP逆流管道的形式化设计:握手代数的案例研究
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656313
M. B. Josephs, P. Lucassen, J. T. Udding, T. Verhoeff
{"title":"Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra","authors":"M. B. Josephs, P. Lucassen, J. T. Udding, T. Verhoeff","doi":"10.1109/ASYNC.1994.656313","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656313","url":null,"abstract":"Two recent developments in asynchronous circuit design are explored by means of a case study (polynomial division) in digital signal processing. The first development is a new formal method, the handshake algebra of M.B. Josephs, J.T. Udding and J.T. Yantchev (1993), that is suitable for specifying, deriving, and verifying circuits that follow a handshaking protocol. The second development is an architecture, counterflow pipelines, that R.F. Sproull (1994) has recently suggested, which is attractive to implement asynchronously.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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