Partial scan test for asynchronous circuits illustrated on a DCC error corrector

Abstract

We present a design-for-testability method for asynchronous circuits based on partial scan. More specifically, we investigate how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and we show that asynchronous partial scan design can be approached as a high-level design activity. The method is demonstrated on an asynchronous error corrector for the DCC player. It has been used effectually in the production and application-mode tests of this 155 k transistor chip-set. In particular, it has led to high 99.9% stuck-at output fault coverage in short 64 msec test time at the expense of less than 3% additional area.