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Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems最新文献

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An asynchronous pipelined lattice structure filter 一个异步流水线点阵结构滤波器
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656301
U. Cummings, Andrew Lines, Alain J. Martin
{"title":"An asynchronous pipelined lattice structure filter","authors":"U. Cummings, Andrew Lines, Alain J. Martin","doi":"10.1109/ASYNC.1994.656301","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656301","url":null,"abstract":"We derive an asynchronous, delay-insensitive CMOS circuit to implement a finite impulse response lattice structure filter. Simulation indicates a performance in the range of 380 million multiplications and 980 million additions per second in Hewlett-Packard's 0.8 /spl mu/m technology (/spl lambda/=0.5 /spl mu/m). We obtain high throughput by using deep pipelines and buffering the carry chains of adders and multipliers. Our work demonstrates that formal design can easily yield circuits which are safe and fast.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115697183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs 从安全的简单信号转换图合成亚稳健自定时电路
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656290
Edwin G. Y. Chung, L. Kleeman
{"title":"Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs","authors":"Edwin G. Y. Chung, L. Kleeman","doi":"10.1109/ASYNC.1994.656290","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656290","url":null,"abstract":"A technique for the synthesis of metastable-robust self-timed digital circuits from live safe simple signal transition graphs (LSS STGs) is described. In this technique, the set of non-input choices and their related signals are first identified. Metastable behaviour of circuit elements implementing these signals is next contained using differential threshold buffers (DTB), thus preventing circuit malfunctions. An LSS STG is implemented as an example.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127279775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An event controlled reconfigurable multi-chip FFT 一个事件控制的可重构多芯片FFT
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656304
S. Morton, S. Appleton, M. Liebelt
{"title":"An event controlled reconfigurable multi-chip FFT","authors":"S. Morton, S. Appleton, M. Liebelt","doi":"10.1109/ASYNC.1994.656304","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656304","url":null,"abstract":"This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continuous streams of transforms of up to 65536 points. The control structure is asynchronous, and hence a fast, very low power, slew-free environment is provided. Aspects of the event controlled methodology used for this, and other designs, is also presented.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120958821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Verification of the speed-independent circuits by STG unfoldings 通过STG展开验证速度无关电路
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656287
A. Kondratyev, A. Taubin
{"title":"Verification of the speed-independent circuits by STG unfoldings","authors":"A. Kondratyev, A. Taubin","doi":"10.1109/ASYNC.1994.656287","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656287","url":null,"abstract":"In this paper we show how to analyze an arbitrary STG for the speed-independence property. The idea of analysis is based on the STG unfolding into an acyclic graph. The improved method of unfolding is suggested, in which the size of the obtained description is always less (or equal in the case of a fully sequential process) than the size of a corresponding state graph. Based on this method the verification algorithms of STG analysis are developed. These algorithms are polynomial from the size of STG unfolding. Their efficiency is considered on the set of benchmarks.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication links 一种延迟控制的锁相环，用于减少同步/异步通信链路中的时序误差
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656307
J. Chappel, S. Zaky
{"title":"A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication links","authors":"J. Chappel, S. Zaky","doi":"10.1109/ASYNC.1994.656307","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656307","url":null,"abstract":"Asynchronous design techniques offer many advantages and are being increasingly used in digital systems. As a result, reliable synchronous/asynchronous communication links are needed. A handshaking protocol is often used in such links. However, errors due to metastability occur when a control signal changes too close to the active clock edge of the synchronous system. This paper introduces a simple, delay-controlled phase-locked loop that dynamically adjusts the timing of the control signals to avoid metastability. The proposed scheme is based on injecting a reference signal derived from the clock into the handshake loop. The injected signal induces changes in delay that provide the requisite feedback mechanism. Both simulation and experimental results are given in the paper. They show that stable operation can be achieved over a wide range of parameters.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122547210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient building blocks for delay insensitive circuits 延迟不敏感电路的有效构建模块
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656312
Priyadarsan Patra, D. Fussell
{"title":"Efficient building blocks for delay insensitive circuits","authors":"Priyadarsan Patra, D. Fussell","doi":"10.1109/ASYNC.1994.656312","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656312","url":null,"abstract":"We introduce a new set of primitive elements for delay-insensitive (DI) circuit design. This set is shown to be universal and minimal, that is, any DI circuit can be constructed using only these primitives, and no proper subset of them is sufficient for constructing all such circuits. We give area efficient fast, and robust switch-level implementations of key primitives and show how to use them to construct other DI circuit elements commonly found in the literature.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134030860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Delay-insensitive solutions to the committee problem 延迟不敏感的委员会问题的解决方案
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656315
I. Benko, J. Ebergen
{"title":"Delay-insensitive solutions to the committee problem","authors":"I. Benko, J. Ebergen","doi":"10.1109/ASYNC.1994.656315","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656315","url":null,"abstract":"The committee problem involves the specification and design of a scheduler for committee meetings. It is a general resource allocation problem that combines both synchronization and mutual exclusion. We give a simple specification of a scheduler and present three delay-insensitive implementations. Our last implementation contains a high degree of parallelism and is simpler than previously proposed implementations.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124953889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A technique for estimating power in asynchronous circuits 一种估算异步电路功率的技术
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656309
P. Kudva, V. Akella
{"title":"A technique for estimating power in asynchronous circuits","authors":"P. Kudva, V. Akella","doi":"10.1109/ASYNC.1994.656309","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656309","url":null,"abstract":"In this paper we investigate the problem of estimating power consumption in an asynchronous (clock-less) circuit. Specifically, we examine the differences in power estimation in synchronous and asynchronous circuits and propose to integrate and extend the recent work by Devadas, Ghosh, and Keutzer to self-timed circuits. A Petri net based abstraction for self-timed circuits is used to derive algorithms for power estimation. The analysis is performed on the embedded discrete time Markov chain in the reachability graph of the Petri net.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123756556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Bounded delay timing analysis of a class of CSP programs with choice 一类具有选择的CSP规划的有界延迟时序分析
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656281
H. Hulgaard, S. Burns
{"title":"Bounded delay timing analysis of a class of CSP programs with choice","authors":"H. Hulgaard, S. Burns","doi":"10.1109/ASYNC.1994.656281","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656281","url":null,"abstract":"We extend our technique for determining exact time separation of events in systems with just concurrency to a restricted but still useful class of systems with both choice and concurrency. Such a system is described using a CSP program (including Martin's probe operator) with the restrictions that the communication behavior is data-independent, that there is no OR-causality, and that guard selection is either completely free or mutually exclusive. Such a CSP program is transformed into a safe Petri net. Interval time delays are specified on the places of the net. The timing analysis we perform is, for all possible timed executions of the system, determine the extreme separations in time for all occurrences of specified events. We formally define this problem, propose an algorithm for its solution, and apply the algorithm to an example program.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125409255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Performance comparison of asynchronous adders 异步加法器的性能比较
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI: 10.1109/ASYNC.1994.656299
M. Franklin, Tienyo Pan
{"title":"Performance comparison of asynchronous adders","authors":"M. Franklin, Tienyo Pan","doi":"10.1109/ASYNC.1994.656299","DOIUrl":"https://doi.org/10.1109/ASYNC.1994.656299","url":null,"abstract":"In asynchronous systems, average function delays principally govern overall throughput. This paper compares the performance of six adder designs with respect to their average delays. Our results show that asynchronous adders (32 or 64-bits) with a hybrid structure (e.g., carry-select adders) run 20-40% faster than simple ripple-carry adders. Hybrid adders also outperform high-cost, strictly synchronous conditional-sum adders.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123406237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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