延迟不敏感电路的有效构建模块

Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1994-11-03 DOI:10.1109/ASYNC.1994.656312

Priyadarsan Patra, D. Fussell

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引用次数: 27

摘要

本文介绍了一套新的用于延迟不敏感电路设计的基本元件。证明了这个集合是泛最小的，即任何DI电路都可以只用这些原语来构造，并且它们的适当子集不足以构造所有这样的电路。我们给出了区域高效、快速、健壮的开关级关键原语实现，并展示了如何使用它们来构建文献中常见的其他DI电路元件。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Efficient building blocks for delay insensitive circuits

We introduce a new set of primitive elements for delay-insensitive (DI) circuit design. This set is shown to be universal and minimal, that is, any DI circuit can be constructed using only these primitives, and no proper subset of them is sufficient for constructing all such circuits. We give area efficient fast, and robust switch-level implementations of key primitives and show how to use them to construct other DI circuit elements commonly found in the literature.

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来源期刊

Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems

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