Verification of the speed-independent circuits by STG unfoldings

Abstract

In this paper we show how to analyze an arbitrary STG for the speed-independence property. The idea of analysis is based on the STG unfolding into an acyclic graph. The improved method of unfolding is suggested, in which the size of the obtained description is always less (or equal in the case of a fully sequential process) than the size of a corresponding state graph. Based on this method the verification algorithms of STG analysis are developed. These algorithms are polynomial from the size of STG unfolding. Their efficiency is considered on the set of benchmarks.