{"title":"基于不同延迟模型的异步电路时序可靠性评估","authors":"M. Kuwako, T. Nanya","doi":"10.1109/ASYNC.1994.656283","DOIUrl":null,"url":null,"abstract":"We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Timing-reliability evaluation of asynchronous circuits based on different delay models\",\"authors\":\"M. Kuwako, T. Nanya\",\"doi\":\"10.1109/ASYNC.1994.656283\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.\",\"PeriodicalId\":114048,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"volume\":\"121 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASYNC.1994.656283\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1994.656283","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Timing-reliability evaluation of asynchronous circuits based on different delay models
We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.