基于不同延迟模型的异步电路时序可靠性评估

M. Kuwako, T. Nanya
{"title":"基于不同延迟模型的异步电路时序可靠性评估","authors":"M. Kuwako, T. Nanya","doi":"10.1109/ASYNC.1994.656283","DOIUrl":null,"url":null,"abstract":"We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Timing-reliability evaluation of asynchronous circuits based on different delay models\",\"authors\":\"M. Kuwako, T. Nanya\",\"doi\":\"10.1109/ASYNC.1994.656283\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.\",\"PeriodicalId\":114048,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"volume\":\"121 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASYNC.1994.656283\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1994.656283","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

我们提出了一种定量的方法来评估异步电路在各种延迟模型下的时序可靠性。使用该度量,我们评估了异步系统的各种构建块的时间可靠性,以及速度性能和硬件成本。最后,给出了设计可靠异步处理器时选择有效延迟模型的指导原则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Timing-reliability evaluation of asynchronous circuits based on different delay models
We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信