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Uniform DC Compact Model for Schottky Barrier and Reconfigurable Field-Effect Transistors 肖特基势垒和可重构场效应晶体管的均匀直流紧凑模型
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437954
C. Roemer, G. Darbandy, M. Schwarz, J. Trommer, A. Heinzig, T. Mikolajick, W. Weber, B. Iñíguez, A. Kloes
{"title":"Uniform DC Compact Model for Schottky Barrier and Reconfigurable Field-Effect Transistors","authors":"C. Roemer, G. Darbandy, M. Schwarz, J. Trommer, A. Heinzig, T. Mikolajick, W. Weber, B. Iñíguez, A. Kloes","doi":"10.1109/LAEDC51812.2021.9437954","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437954","url":null,"abstract":"This paper presents a closed-form, physics-based compact model which is used to calculate the DC characteristics of double gate Schottky barrier field-effect transistors (SBFETs) and reconfigurable field-effect transistors (RFETs). Therefore, the model calculates the drain current which consists of field emission through the Schottky barrier and thermionic emission over the barrier. In order to validate the model, this paper shows results for the calculated current in SBFETs and RFETs compared to transfer characteristics of simulated devices and measurements, which show a good agreement.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114063782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysing the Efficiency Enhancement of Indoor Organic Photovoltaic using Impedance Spectroscopy Technique 利用阻抗光谱技术分析室内有机光伏的增效效果
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437965
Alfonsina Abat Amelenan Torimtubun, J. Pallarès, L. Marsal
{"title":"Analysing the Efficiency Enhancement of Indoor Organic Photovoltaic using Impedance Spectroscopy Technique","authors":"Alfonsina Abat Amelenan Torimtubun, J. Pallarès, L. Marsal","doi":"10.1109/LAEDC51812.2021.9437965","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437965","url":null,"abstract":"Impedance spectroscopy (IS) has been widely applied to study organic photovoltaic (OPV) device performance in the past few decades. IS allows the characterization in a broad range of time scales to extract information about internal process occurred within OPV. However, most of the characterization were performed under standard AM 1.5G illumination–known as outdoor performance. Recently, the potential application OPV under indoor energy harvesting have attracted great interest. In this work, IS analysis was used to study the reason of power conversion efficiency (PCE) enhancement in indoor performance (LED 2700 K, 250 – 2000 lux) of inverted OPV based on bulk heterojunction PTB7-Th:PC70BM with the device structure of ITO/TiOx/PTB7-Th:PC70BM/V2O5/Ag in comparison with the outdoor performance counterparts.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116603315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive Comparison of Fabricated 1.6-kV Punch-Through Design Ni/n-SiC Schottky Barrier Diode with Ar+ Implant Edge Termination and Heterojunction p-NiO/n-SiC Diode 制备1.6 kv Ar+植入端端击穿设计Ni/n-SiC肖特基势垒二极管与异质结p-NiO/n-SiC二极管的综合比较
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437747
Atsushi Shimbori, H. Wong, A. Huang
{"title":"Comprehensive Comparison of Fabricated 1.6-kV Punch-Through Design Ni/n-SiC Schottky Barrier Diode with Ar+ Implant Edge Termination and Heterojunction p-NiO/n-SiC Diode","authors":"Atsushi Shimbori, H. Wong, A. Huang","doi":"10.1109/LAEDC51812.2021.9437747","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437747","url":null,"abstract":"A comprehensive comparison of a punch-through Ni/SiC Schottky diode with Ar+ implant edge termination and heterojunction NiO/SiC diode were conducted through fabrication, electrical evaluation, TCAD simulation analysis and reverse recovery evaluation. Both fabricated diodes exhibit high breakdown voltage of 1595V, utilizing a punch-through design. The heterojunction NiO/SiC diode has shown ×0.5 less reverse leakage current than the Ni/SiC Schottky diode due to higher barrier height. The Ni/SiC Schottky diode, on the other hand, has shown 90% less reverse recovery time, indicating a small degree of minority carrier injection for the heterojunction NiO/SiC diode.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134076136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Versatile BiCMOS Technology Platform for the Low-cost Integration of Multi-purpose Applications 多用途应用低成本集成的多功能BiCMOS技术平台
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437969
T. Suligoj, J. Žilak, Željko Osrečki, M. Koričić
{"title":"Versatile BiCMOS Technology Platform for the Low-cost Integration of Multi-purpose Applications","authors":"T. Suligoj, J. Žilak, Željko Osrečki, M. Koričić","doi":"10.1109/LAEDC51812.2021.9437969","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437969","url":null,"abstract":"Integration of Horizontal Current Bipolar Transistor (HCBT) with CMOS requires fewer additional fabrication steps as compared to vertical-current bipolar devices having state-of-the-art electrical characteristics both in demonstrated implanted-base technology and in simulated SiGe-base technology. HCBT’s noise characteristics and large-signal performance for RF applications is tuned by the collector region design and the optimum device for each application is identified and characterized. High-voltage transistors are demonstrated in HCBT technology with BVCEO from 2.8 V to above 70 V enabling the integration RF and power management and other high-voltage circuits. The HCBT with SiGe base exhibits a potential of further improving the highest-performance vertical-current SiGe HBTs and overcoming their integration limitations with CMOS due to geometrical and material incompatibility.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128320230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Simple Method for Seamless Integration of CMOS Chips with Microfluidics 一种CMOS芯片与微流体无缝集成的简单方法
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437938
D. Barrettino
{"title":"A Simple Method for Seamless Integration of CMOS Chips with Microfluidics","authors":"D. Barrettino","doi":"10.1109/LAEDC51812.2021.9437938","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437938","url":null,"abstract":"This paper describes a simple method for seamless integration of a CMOS chip with typical centimeter-scale microfluidics. A simple planar mold is used to cast PDMS around the perimeter of a single die-cut CMOS chip (5 mm x 6 mm) mounted on a standard chip package (DIL-48, 1 cm x 4 cm). The casting results in a contiguous intersection between the exposed chip surface and the co-planar PDMS that extends across the package. A microfluidic channel added to the package extends across the chip boundary, while fluid in the channel is in direct contact with the chip surface. The large platform of this chip package allows fluid connections to be located far from the chip to prevent interference with optical detection, and thin-layer PDMS microfluidics (about 350µm) created by casting are compatible with short-working-distance microscope objectives. This method requires no sophisticated chip post-processing, accommodates individual CMOS chips, and expands the footprint available for microfluidics. Temporary bonding using PDMS as adhesive allows removal of the microfluidics and recovery of the chip and planarized package. This is a simple and reversible method that is well-suited for prototyping devices using large footprint disposable fluidics and small high-value CMOS chips.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131100849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors 无结纳米线晶体管跨电容的解析紧凑模型
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437910
M. Pavanello, T. A. Ribeiro, A. Cerdeira, F. Avila-Herrera
{"title":"Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors","authors":"M. Pavanello, T. A. Ribeiro, A. Cerdeira, F. Avila-Herrera","doi":"10.1109/LAEDC51812.2021.9437910","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437910","url":null,"abstract":"This paper presents the proposal of a compact analytical model for the transcapacitances of long-channel triple gate junctionless nanowire transistors. The model is validated using comparisons against 3D TCAD simulations showing very good agreement, with continuous transitions between all regions of operation.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"426 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127603858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Direct extraction of solar cell model parameters using optimization methods 利用优化方法直接提取太阳能电池模型参数
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437951
A. Ortiz-Conde, O. Trejo, F. García-Sánchez
{"title":"Direct extraction of solar cell model parameters using optimization methods","authors":"A. Ortiz-Conde, O. Trejo, F. García-Sánchez","doi":"10.1109/LAEDC51812.2021.9437951","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437951","url":null,"abstract":"This article reviews and appraises various fitting parameter extraction methods for solar cells modeled with 5 parameters. The current of illuminated photovoltaic panels and solar cells are customarily described by the single diode model, which contains a diode, a current source, a series resistance and a parallel conductance. This simple model with only 5 parameters provides reasonable accuracy. In this work, we carry out a comparative review of several parameter extraction methods using many data points, since methods based on fewer data points are more prone to measurement error. Among the methods tested in this benchmark are the implicit fitting, the direct optimization of the current (vertical fit) using the Lambert W function, and the Co-content method, which is based on fitting the integral of current with respect to voltage. We also evaluate the direct optimization of the voltage (lateral fit) using the Lambert W function. The results demonstrate that, regarding convergence reliability for a large range of initial values, the best procedure is the Co-content method, which is based on the use of a quadratic equation for fitting. We tested the different methods on the same experimental data of a solar cell as well as PV modules measured by NREL.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133624749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fully/partially suspended gate SiC-based FET for power applications 用于功率应用的全/部分悬浮栅硅基场效应管
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437932
S. Nayak, S. Lodha, S. Ganguly
{"title":"Fully/partially suspended gate SiC-based FET for power applications","authors":"S. Nayak, S. Lodha, S. Ganguly","doi":"10.1109/LAEDC51812.2021.9437932","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437932","url":null,"abstract":"A fully/partially suspended gate can overcome the issue of low channel mobility due to interface traps at the Silicon Carbide (SiC) and Silicon Dioxide (SiO2) interface of a SiC-based DMOS. TCAD simulations (with a deck calibrated to experimental data for SiC) confirms that a suspended gate structure with Air or hybrid dielectrics (stack of Air and SiO2) provides substantial performance enhancement. The device design (Dielectric spacing) is optimized via simulations. With experimentally reported densities of interface traps the output current indicate that they have a negligible effect on the device performance.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An affordable post-silicon testing framework applied to a RISC-V based microcontroller 一个经济实惠的后硅测试框架应用于基于RISC-V的微控制器
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437939
R. Molina-Robles, R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío, A. Arnaud
{"title":"An affordable post-silicon testing framework applied to a RISC-V based microcontroller","authors":"R. Molina-Robles, R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío, A. Arnaud","doi":"10.1109/LAEDC51812.2021.9437939","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437939","url":null,"abstract":"The RISC-V architecture is a very attractive option for developing application specific systems needing an affordable yet efficient central processing unit. Post-silicon validation on RISC-V applications has been done in industry for a while, however documentation is scarce. This paper proposes a practical low-cost post-silicon testing framework applied to a RISC-V RV32I based microcontroller. The framework uses FPGA-based emulation as a cornerstone to test the microcontroller before and after its fabrication. The platform only requires a handful of elements like the FPGA, a PC, the fabricated chip and some discrete components, without losing the capacity to functionally validate the design under test and save development testing time by using a re-utilize philosophy.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"217 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133878114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of Calibration Methods and RF Probes on the RF Characterization of 28FD-SOI MOSFET 校准方法和射频探针对28FD-SOI MOSFET射频特性的影响
2021 IEEE Latin America Electron Devices Conference (LAEDC) Pub Date : 2021-04-19 DOI: 10.1109/LAEDC51812.2021.9437917
Karthi Pradeep, M. Deng, B. Dormieu, P. Scheer, M. D. Matos, T. Zimmer, S. Frégonèse
{"title":"Influence of Calibration Methods and RF Probes on the RF Characterization of 28FD-SOI MOSFET","authors":"Karthi Pradeep, M. Deng, B. Dormieu, P. Scheer, M. D. Matos, T. Zimmer, S. Frégonèse","doi":"10.1109/LAEDC51812.2021.9437917","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437917","url":null,"abstract":"This work focuses on the characterization of 28nm FD-SOI NMOS transistors, in order to study the effect of the calibration techniques employed and the overall measurement environment in the frequency range of 1 – 110 GHz. Comparison is made between the off-wafer SOLT calibration and on-wafer TRL calibration, both followed by de-embedding. The transistor as well as the Open and Short de-embedding structures are characterized to extract the transistor RF figure of merit fT, and the compact model parameters Cgg and gm. Measurements are also repeated with different RF probes (Cascade Infinity and Picoprobe). The results obtained are compared to simulations with the Leti-UTSOI2 model for FD-SOI and conclusions are drawn.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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