一个经济实惠的后硅测试框架应用于基于RISC-V的微控制器

R. Molina-Robles, R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío, A. Arnaud
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引用次数: 2

摘要

RISC-V架构对于开发需要负担得起且高效的中央处理器的特定应用系统来说是一个非常有吸引力的选择。RISC-V应用的后硅验证已经在工业中进行了一段时间,但是文档很少。本文提出了一个实用的低成本后硅测试框架,应用于基于RISC-V RV32I的微控制器。该框架采用基于fpga的仿真作为基石,在微控制器制造前后对其进行测试。该平台只需要FPGA、PC、预制芯片和一些分立组件等少数元素,而不会失去在测试中对设计进行功能验证的能力,并通过使用重用理念节省开发测试时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An affordable post-silicon testing framework applied to a RISC-V based microcontroller
The RISC-V architecture is a very attractive option for developing application specific systems needing an affordable yet efficient central processing unit. Post-silicon validation on RISC-V applications has been done in industry for a while, however documentation is scarce. This paper proposes a practical low-cost post-silicon testing framework applied to a RISC-V RV32I based microcontroller. The framework uses FPGA-based emulation as a cornerstone to test the microcontroller before and after its fabrication. The platform only requires a handful of elements like the FPGA, a PC, the fabricated chip and some discrete components, without losing the capacity to functionally validate the design under test and save development testing time by using a re-utilize philosophy.
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