Fully/partially suspended gate SiC-based FET for power applications

Abstract

A fully/partially suspended gate can overcome the issue of low channel mobility due to interface traps at the Silicon Carbide (SiC) and Silicon Dioxide (SiO2) interface of a SiC-based DMOS. TCAD simulations (with a deck calibrated to experimental data for SiC) confirms that a suspended gate structure with Air or hybrid dielectrics (stack of Air and SiO2) provides substantial performance enhancement. The device design (Dielectric spacing) is optimized via simulations. With experimentally reported densities of interface traps the output current indicate that they have a negligible effect on the device performance.