{"title":"一种CMOS芯片与微流体无缝集成的简单方法","authors":"D. Barrettino","doi":"10.1109/LAEDC51812.2021.9437938","DOIUrl":null,"url":null,"abstract":"This paper describes a simple method for seamless integration of a CMOS chip with typical centimeter-scale microfluidics. A simple planar mold is used to cast PDMS around the perimeter of a single die-cut CMOS chip (5 mm x 6 mm) mounted on a standard chip package (DIL-48, 1 cm x 4 cm). The casting results in a contiguous intersection between the exposed chip surface and the co-planar PDMS that extends across the package. A microfluidic channel added to the package extends across the chip boundary, while fluid in the channel is in direct contact with the chip surface. The large platform of this chip package allows fluid connections to be located far from the chip to prevent interference with optical detection, and thin-layer PDMS microfluidics (about 350µm) created by casting are compatible with short-working-distance microscope objectives. This method requires no sophisticated chip post-processing, accommodates individual CMOS chips, and expands the footprint available for microfluidics. Temporary bonding using PDMS as adhesive allows removal of the microfluidics and recovery of the chip and planarized package. This is a simple and reversible method that is well-suited for prototyping devices using large footprint disposable fluidics and small high-value CMOS chips.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Simple Method for Seamless Integration of CMOS Chips with Microfluidics\",\"authors\":\"D. Barrettino\",\"doi\":\"10.1109/LAEDC51812.2021.9437938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a simple method for seamless integration of a CMOS chip with typical centimeter-scale microfluidics. A simple planar mold is used to cast PDMS around the perimeter of a single die-cut CMOS chip (5 mm x 6 mm) mounted on a standard chip package (DIL-48, 1 cm x 4 cm). The casting results in a contiguous intersection between the exposed chip surface and the co-planar PDMS that extends across the package. A microfluidic channel added to the package extends across the chip boundary, while fluid in the channel is in direct contact with the chip surface. The large platform of this chip package allows fluid connections to be located far from the chip to prevent interference with optical detection, and thin-layer PDMS microfluidics (about 350µm) created by casting are compatible with short-working-distance microscope objectives. This method requires no sophisticated chip post-processing, accommodates individual CMOS chips, and expands the footprint available for microfluidics. Temporary bonding using PDMS as adhesive allows removal of the microfluidics and recovery of the chip and planarized package. This is a simple and reversible method that is well-suited for prototyping devices using large footprint disposable fluidics and small high-value CMOS chips.\",\"PeriodicalId\":112590,\"journal\":{\"name\":\"2021 IEEE Latin America Electron Devices Conference (LAEDC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Latin America Electron Devices Conference (LAEDC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LAEDC51812.2021.9437938\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LAEDC51812.2021.9437938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种将CMOS芯片与典型厘米级微流体无缝集成的简单方法。一个简单的平面模具用于围绕一个模切CMOS芯片(5mm x 6mm)的周长铸造PDMS,该芯片安装在标准芯片封装(dil - 48,1 cm x 4 cm)上。浇铸导致暴露的芯片表面和横跨封装的共面PDMS之间的连续相交。添加到封装中的微流控通道延伸穿过芯片边界,而通道中的流体与芯片表面直接接触。该芯片封装的大平台允许流体连接位于远离芯片的位置,以防止对光学检测的干扰,并且通过铸造产生的薄层PDMS微流体(约350µm)与短工作距离显微镜物镜兼容。这种方法不需要复杂的芯片后处理,可容纳单个CMOS芯片,并扩展可用于微流体的足迹。使用PDMS作为粘合剂的临时粘合可以去除微流体并恢复芯片和扁平封装。这是一种简单且可逆的方法,非常适合使用大尺寸一次性流体和小型高价值CMOS芯片的原型设备。
A Simple Method for Seamless Integration of CMOS Chips with Microfluidics
This paper describes a simple method for seamless integration of a CMOS chip with typical centimeter-scale microfluidics. A simple planar mold is used to cast PDMS around the perimeter of a single die-cut CMOS chip (5 mm x 6 mm) mounted on a standard chip package (DIL-48, 1 cm x 4 cm). The casting results in a contiguous intersection between the exposed chip surface and the co-planar PDMS that extends across the package. A microfluidic channel added to the package extends across the chip boundary, while fluid in the channel is in direct contact with the chip surface. The large platform of this chip package allows fluid connections to be located far from the chip to prevent interference with optical detection, and thin-layer PDMS microfluidics (about 350µm) created by casting are compatible with short-working-distance microscope objectives. This method requires no sophisticated chip post-processing, accommodates individual CMOS chips, and expands the footprint available for microfluidics. Temporary bonding using PDMS as adhesive allows removal of the microfluidics and recovery of the chip and planarized package. This is a simple and reversible method that is well-suited for prototyping devices using large footprint disposable fluidics and small high-value CMOS chips.