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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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An AC-3/MPEG multi-standard audio decoder IC 一个AC-3/MPEG多标准音频解码器IC
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606622
S. Li, J. Rowlands, P. Ng, M. Gill, D.S. Youm, D. Kam, S. Song, P. Look
{"title":"An AC-3/MPEG multi-standard audio decoder IC","authors":"S. Li, J. Rowlands, P. Ng, M. Gill, D.S. Youm, D. Kam, S. Song, P. Look","doi":"10.1109/CICC.1997.606622","DOIUrl":"https://doi.org/10.1109/CICC.1997.606622","url":null,"abstract":"The emerging digital audio compression technology brings both an opportunity and a new challenge to IC design. High quality multichannel audio is quickly becoming an indispensable part of an entertainment system. The algorithms used in the compression technology result in complex VLSI ICs. The work presented in this paper is about the design of a dedicated, high precision, and low cost AC3/MPEG multi-standard audio decoder. The audio IC's hardware and software architecture, as well as design and simulation/verification methodology are discussed in detail.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126692676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Making precise at-speed timing measurements via boundary-scan 通过边界扫描进行精确的高速定时测量
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606614
T. Almy
{"title":"Making precise at-speed timing measurements via boundary-scan","authors":"T. Almy","doi":"10.1109/CICC.1997.606614","DOIUrl":"https://doi.org/10.1109/CICC.1997.606614","url":null,"abstract":"IEEE 1149.1 Boundary-Scan has traditionally been used for continuity and low speed functional testing of integrated circuits. The boundary-scan RUNBIST instruction allows Built-In Self Test for functional testing at full clock speeds. This paper describes an approach that uses the RUNBIST instruction to make timing measurements with a resolution 32 times smaller than the clock period while doing at-speed testing. Measurement commands and results are transmitted via boundary-scan.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124067240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Universal guideline for CMOS I/O signal integrity CMOS I/O信号完整性通用指南
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606646
T. Gabara, J. Harrington, R. Yan
{"title":"Universal guideline for CMOS I/O signal integrity","authors":"T. Gabara, J. Harrington, R. Yan","doi":"10.1109/CICC.1997.606646","DOIUrl":"https://doi.org/10.1109/CICC.1997.606646","url":null,"abstract":"BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6.25-GHz low DC power low-noise amplifier in SiGe 6.25 ghz低直流功率低噪声SiGe放大器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606608
H. Ainspan, M. Soyuer, J. Plouchart, J. Burghartz
{"title":"A 6.25-GHz low DC power low-noise amplifier in SiGe","authors":"H. Ainspan, M. Soyuer, J. Plouchart, J. Burghartz","doi":"10.1109/CICC.1997.606608","DOIUrl":"https://doi.org/10.1109/CICC.1997.606608","url":null,"abstract":"A 6.25-GHz monolithic low-noise amplifier (LNA) with a minimum noise figure of 2.2 dB and an associated gain of 20.4 dB implemented in a standard SiGe bipolar technology is presented. The 50-ohm noise figure is 3.5 dB with S21 of 18.3 dB. The circuit dissipates 9.4 mW from a 2.5-V supply (6.4 mW in the gain stages). The LNA's figure of merit gain/(P/sub DC//spl times/NF) of 0.56 mW/sup -1/ exceeds those of recently published 5 to 6 GHz GaAs MESFET and HBT LNA's.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115048096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
2-/spl mu/m, 1.6-mW gated-g/sub m/ sampler with 72 dB SFDR at 160 Ms/s and 320.25-MHz f/sub in/ 2-/spl mu/m, 1.6 mw门控-g/sub /m /采样器，在160 Ms/s和320.25 mhz f/sub / in/下具有72 dB SFDR
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606586
S. C. Munroe
{"title":"2-/spl mu/m, 1.6-mW gated-g/sub m/ sampler with 72 dB SFDR at 160 Ms/s and 320.25-MHz f/sub in/","authors":"S. C. Munroe","doi":"10.1109/CICC.1997.606586","DOIUrl":"https://doi.org/10.1109/CICC.1997.606586","url":null,"abstract":"The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a high-speed, wideband sampler based upon a charge-domain gated-gm cell that has a measured SFDR of 72 dB at 160 Ms/s and 320.25-MHz input frequency. This performance is achieved at 2% of the power and 4% of the area of a recently-released high-performance but slower sampler. Simulations indicate that far higher performance is possible in a more optimized circuit.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116943680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.4 GHz monolithic mixer for wireless LAN applications 用于无线局域网应用的2.4 GHz单片混频器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606610
K. Fong, R. Meyer
{"title":"A 2.4 GHz monolithic mixer for wireless LAN applications","authors":"K. Fong, R. Meyer","doi":"10.1109/CICC.1997.606610","DOIUrl":"https://doi.org/10.1109/CICC.1997.606610","url":null,"abstract":"A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132442810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Performance improvement of a thick field oxide ESD protection circuit by halo implant 光晕植入改善厚场氧化ESD保护电路的性能
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606580
P. Gilbert, P. Tsui, Shih-Wei Sun, S. Jamison, J. Miller
{"title":"Performance improvement of a thick field oxide ESD protection circuit by halo implant","authors":"P. Gilbert, P. Tsui, Shih-Wei Sun, S. Jamison, J. Miller","doi":"10.1109/CICC.1997.606580","DOIUrl":"https://doi.org/10.1109/CICC.1997.606580","url":null,"abstract":"Optimization of a sub-0.5 /spl mu/m ESD protection circuit using halo implant is described. A p-type halo implant significantly improves the ESD robustness of a high performance I/O circuit as noted by Human Body Model (HBM) test results. The improved ESD performance is directly attributed to the ability of the halo implanted Thick Field Oxide (TFO) device to inhibit the turn-on of the n-channel output buffer during an ESD event. Improved ESD performance is achieved without the use of additional series resistance and with no increase in device area. The results represent the first time transmission-line pulse generator (TLPG) analysis has been used on a fully synthesized I/O circuit to predict wafer level ESD performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A reusable embedded DRAM macrocell 一种可重复使用的嵌入式DRAM宏单元
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606642
P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger
{"title":"A reusable embedded DRAM macrocell","authors":"P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger","doi":"10.1109/CICC.1997.606642","DOIUrl":"https://doi.org/10.1109/CICC.1997.606642","url":null,"abstract":"A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131777782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS 在可变阈值电压CMOS中采用可变电源电压方案的300 MIPS/W RISC核心处理器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606694
K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Kuroda
{"title":"A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS","authors":"K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Kuroda","doi":"10.1109/CICC.1997.606694","DOIUrl":"https://doi.org/10.1109/CICC.1997.606694","url":null,"abstract":"A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
A Dolby AC-3/MPEG1 audio decoder core suitable for audio/visual system integration 一款适合音视频系统集成的杜比AC-3/MPEG1音频解码器内核
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606621
H. Sakamoto, Y. Shibuya, H. Takano, O. Kitabatake, I. Tamitani
{"title":"A Dolby AC-3/MPEG1 audio decoder core suitable for audio/visual system integration","authors":"H. Sakamoto, Y. Shibuya, H. Takano, O. Kitabatake, I. Tamitani","doi":"10.1109/CICC.1997.606621","DOIUrl":"https://doi.org/10.1109/CICC.1997.606621","url":null,"abstract":"A synthesizable Dolby AC-3/MPEG1 audio decoder core has been developed for use in audio/visual system LSIs. In order to optimize the core both in size and power consumption, it employs a dedicated design approach rather than a DSP approach. Moreover, the core is designed to operate at 27 MHz, which is slower than reported DSP implementations, and is useful for integration with digital video decoders. An experimental decoder chip has successfully fabricated using a 0.35 um cell-based CMOS technology, to evaluate the AC-3/MPEG1 audio decoder core. Because the chip integrates a 61 Kbit RAM with the core, it can achieve 5.1 ch AC-3 decoding by single-chip. The developed and evaluated decoder core is utilized in variable digital audio/video system chips, including single-chip DVD A/V decoders.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125739922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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