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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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A high performance, high density sea of modules FPGA architecture 一种高性能、高密度的模块海FPGA架构
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606683
K. El-Ayat, S. Kaptanoglu, R. Chan, J. Lien, W. Plants, R. Asayesh, L. Cheng, R. Lambertson, G. Bakker, A. El-Toukhy, M. Chew, R. Gopissety, W. Miller, S. Ku
{"title":"A high performance, high density sea of modules FPGA architecture","authors":"K. El-Ayat, S. Kaptanoglu, R. Chan, J. Lien, W. Plants, R. Asayesh, L. Cheng, R. Lambertson, G. Bakker, A. El-Toukhy, M. Chew, R. Gopissety, W. Miller, S. Ku","doi":"10.1109/CICC.1997.606683","DOIUrl":"https://doi.org/10.1109/CICC.1997.606683","url":null,"abstract":"Functionality and flexibility has been significantly enhanced with this novel sea of modules FPGA architecture. It includes a new improved logic cell, high performance interconnect architecture and full featured fracturable flip flops. The architecture is designed for high in system performance as well as low cost user programmable implementations. A flexible high performance I/O architecture complements the architecture with high performance input/output delays. A modular architecture and design methodology allows quick proliferation to multiple families while tailoring the individual family characteristics to quickly serve a particular market segment. The family uses a novel metal to metal antifuse technology that affords high performance, scalability and cost reduction.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic floating body control SOI CMOS circuits for power managed multimedia ULSIs 用于电源管理多媒体ulsi的动态浮体控制SOI CMOS电路
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606626
F. Morishita, M. Tsukude, K. Arimoto
{"title":"Dynamic floating body control SOI CMOS circuits for power managed multimedia ULSIs","authors":"F. Morishita, M. Tsukude, K. Arimoto","doi":"10.1109/CICC.1997.606626","DOIUrl":"https://doi.org/10.1109/CICC.1997.606626","url":null,"abstract":"A novel body potential controlling technique for floating SOI CMOS circuits is proposed and verified. High speed operation is realized with a small chip size by using body-floating SOI transistors. By using this technique, the threshold voltage of the body-floating transistors is varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced less than 1/10th compared to the non-control operation of the body potential and operates at high speed during the active period. There is no access penalty for the recovery operation from the standby mode. This technique supports sub 1 V operation, which is required for future battery operated devices with wide range covering.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117304017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform 离散小波变换高效VLSI架构的设计与实现
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606620
Chu Yu, Chien-An Hsieh, Sao-Jie Chen
{"title":"Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform","authors":"Chu Yu, Chien-An Hsieh, Sao-Jie Chen","doi":"10.1109/CICC.1997.606620","DOIUrl":"https://doi.org/10.1109/CICC.1997.606620","url":null,"abstract":"Since the discrete wavelet transform (DWT) is a kind of multi-rate transform, it is difficult to design an optimal computation-time architecture for the DWT. In this paper, we propose a highly efficient VLSI architecture for the 1-D DWT decomposition. This architecture contains two stages of systolic decimation filter banks to guarantee a high throughput and an optimal computation time. Using this architecture, N-point samples with J resolution levels can be computed in N clock cycles spending only JL registers, where L denotes filter length. Due to its regular structure, this architecture can be easily scaled up with the tap size of the filters and the number of octaves. The performance of the proposed architecture will be verified by the successful implementation of a 4-tap 3-octave DWT VLSI chip.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132476464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A stochastic wire length distribution for gigascale integration (GSI) 千兆级集成(GSI)的随机导线长度分布
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606603
Jeffrey A. Davis, Vivek De, James D. Meindl
{"title":"A stochastic wire length distribution for gigascale integration (GSI)","authors":"Jeffrey A. Davis, Vivek De, James D. Meindl","doi":"10.1109/CICC.1997.606603","DOIUrl":"https://doi.org/10.1109/CICC.1997.606603","url":null,"abstract":"Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. This distribution is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132073517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 126
Sensitivity of power dissipation to uncertainties in primary input specification 功率耗散对一次输入规格不确定性的敏感性
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606673
Z.-P. Chen, K. Roy, T. Chou
{"title":"Sensitivity of power dissipation to uncertainties in primary input specification","authors":"Z.-P. Chen, K. Roy, T. Chou","doi":"10.1109/CICC.1997.606673","DOIUrl":"https://doi.org/10.1109/CICC.1997.606673","url":null,"abstract":"To accurately estimate power dissipation, the exact signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching) of primary inputs are assumed to be known. In general, very accurate specification of primary input signal probability and activity may not be available. This in turn may result in uncertainties in average power estimation. In this paper we present a novel and efficient technique to estimate the sensitivity of average power dissipation to input signals using a symbolic estimation technique. Results for benchmark circuits show that power sensitivities can vary widely for different primary inputs of a circuit. Hence, in order to accurately estimate average power dissipation, the sensitive inputs of a circuit have to be specified accurately. We have also developed a Monte-Carlo based technique to estimate power sensitivity which also acts as a figure of merit for the symbolic technique.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Automated low-power technique exploiting multiple supply voltages applied to a media processor 应用于媒体处理器的利用多个电源电压的自动化低功耗技术
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606600
K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida, K. Nogami
{"title":"Automated low-power technique exploiting multiple supply voltages applied to a media processor","authors":"K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida, K. Nogami","doi":"10.1109/CICC.1997.606600","DOIUrl":"https://doi.org/10.1109/CICC.1997.606600","url":null,"abstract":"This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance,.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124628877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 316
A fully-integrated 5 MHz-IF digital FM demodulator 全集成5mhz - if数字调频解调器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606681
Minyoung Song, Jaejin Park, Euro Joe, M. Choe, B. Song
{"title":"A fully-integrated 5 MHz-IF digital FM demodulator","authors":"Minyoung Song, Jaejin Park, Euro Joe, M. Choe, B. Song","doi":"10.1109/CICC.1997.606681","DOIUrl":"https://doi.org/10.1109/CICC.1997.606681","url":null,"abstract":"A 5 MHz-IF digital FM demodulator integrated with a 4th-order bandpass delta-sigma front-end exhibits 74.7 dB SNR, -80.7 dB THD, and 61 dB AM rejection within a 9 kHz message bandwidth. The 0.65 /spl mu/m CMOS chip occupies 3.5 mm/spl times/3.5 mm of active area and consumes 180 mW with 4 V supply and 20 MHz clock.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124306564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A micromachine-based RF low-noise voltage-controlled oscillator 一种基于微机械的射频低噪声压控振荡器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606660
Darrin J. Young, B. E. Boser
{"title":"A micromachine-based RF low-noise voltage-controlled oscillator","authors":"Darrin J. Young, B. E. Boser","doi":"10.1109/CICC.1997.606660","DOIUrl":"https://doi.org/10.1109/CICC.1997.606660","url":null,"abstract":"A voltage-controlled oscillator (VCO) employs an aluminum micromachined variable capacitor for frequency tuning. Unlike conventional varactor diodes, the capacitor is fabricated on a silicon substrate and thus amenable to monolithic integration with a standard IC process. Experimental capacitors achieve a 16% tuning range with a nominal capacitance value of 2 pF and a quality factor above 60 at 1 GHz. A prototype VCO exhibits -107 dBc/Hz phase-noise at 100 kHz offset frequency from the carrier. The center frequency of 714 MHz and 14 MHz tuning range are limited by the test setup.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122153381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Estimation of maximum power and instantaneous current using a genetic algorithm 用遗传算法估计最大功率和瞬时电流
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606601
Yi-Min Jiang, Kwang-Ting Cheng, Angela Krstic
{"title":"Estimation of maximum power and instantaneous current using a genetic algorithm","authors":"Yi-Min Jiang, Kwang-Ting Cheng, Angela Krstic","doi":"10.1109/CICC.1997.606601","DOIUrl":"https://doi.org/10.1109/CICC.1997.606601","url":null,"abstract":"We present a genetic-algorithm-based approach for estimating the maximum power dissipation and instantaneous current through supply lines for CMOS circuits. Our approach can handle large combinational and sequential circuits with arbitrary but known delays. To obtain accurate results we extract the timing and current information from transistor-level and general-delay gate-level simulation. Our experimental results show that the patterns generated by our approach produce on the average a lower bound on the maximum power which is 41% tighter than the one obtained by weighted random patterns for estimating the maximum power. Also, our lower bound for the maximum instantaneous current is 21% tighter as compared to the weighted random patterns.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130160579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
A hardware/software partitioning technique with hierarchical design space exploration 一种具有分层设计空间探索的硬件/软件划分技术
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606592
H. Ondghiri, B. Kaminska, J. Rajski
{"title":"A hardware/software partitioning technique with hierarchical design space exploration","authors":"H. Ondghiri, B. Kaminska, J. Rajski","doi":"10.1109/CICC.1997.606592","DOIUrl":"https://doi.org/10.1109/CICC.1997.606592","url":null,"abstract":"This paper describes a new hardware/software partitioning approach based on a new use of hierarchical modeling. A set of DSP examples are considered for codesign on a specific architecture in order to accelerate their performance on a target architecture including a standard DSP processor running concurrently with a custom SIMD processor. Through this set of examples, we demonstrate the effectiveness that such a use of hierarchy offers; mainly the extent of the design space explored during codesign and the acceleration of DSP algorithms on the target architecture.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124702365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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