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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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Timing abstraction of intellectual property blocks 知识产权块的时序抽象
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606593
S. Venkatesh, R. Palermo, M. Mortazavi, K. Sakallah
{"title":"Timing abstraction of intellectual property blocks","authors":"S. Venkatesh, R. Palermo, M. Mortazavi, K. Sakallah","doi":"10.1109/CICC.1997.606593","DOIUrl":"https://doi.org/10.1109/CICC.1997.606593","url":null,"abstract":"This paper describes a method for creating timing models of large blocks (>5,000 transistors) based on the use of static timing analysis. This method captures the block's propagation delays and the slew rates at its outputs. More importantly, it abstracts all the internal setup, hold, and loop constraints of the block. The resulting block timing model can thus be used as an accurate representation of the block's temporal behavior obviating the need for exposing the block's internal implementation. Block characterization finds application in intellectual property encapsulation and in team design of large timing-constrained chips.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133459380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A gate-level leakage power reduction method for ultra-low-power CMOS circuits 一种超低功耗CMOS电路的门级漏功率降低方法
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606670
J. P. Halter, Farid N. Najm
{"title":"A gate-level leakage power reduction method for ultra-low-power CMOS circuits","authors":"J. P. Halter, Farid N. Najm","doi":"10.1109/CICC.1997.606670","DOIUrl":"https://doi.org/10.1109/CICC.1997.606670","url":null,"abstract":"In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in \"standby\" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a \"low leakage standby state\", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133475910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 291
Analysis and optimization of monolithic inductors and transformers for RF ICs 射频集成电路单片电感和变压器的分析与优化
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606650
A. Niknejad, Robert G. Meyer
{"title":"Analysis and optimization of monolithic inductors and transformers for RF ICs","authors":"A. Niknejad, Robert G. Meyer","doi":"10.1109/CICC.1997.606650","DOIUrl":"https://doi.org/10.1109/CICC.1997.606650","url":null,"abstract":"A fast and accurate approach for analyzing Si IC spiral inductors and transformers is presented. The technique incorporates the substrate in the calculation to fully characterize the devices. Many test structures are fabricated and measured data is used to verify the analysis technique over a broad frequency range. Suitable lumped broadband equivalent circuit models of the structures are presented which can be incorporated into traditional circuit simulators. A custom CAD tool ASITIC is described which is used for the design and optimization of inductors and transformers.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116811198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems 一个完全集成的螺旋lc CMOS压控振荡器设置GSM和DCS-1800系统的预分频器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606654
J. Craninckx, M. Steyaert, Hiroyuki Miyakawa, Kard. Mercierlaan
{"title":"A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems","authors":"J. Craninckx, M. Steyaert, Hiroyuki Miyakawa, Kard. Mercierlaan","doi":"10.1109/CICC.1997.606654","DOIUrl":"https://doi.org/10.1109/CICC.1997.606654","url":null,"abstract":"A set of two VCOs is developed in a 0.4 /spl mu/m CMOS process, using a fully integrated spiral inductor with symmetrical octagonal shape in the resonance LC-tank. One VCO operates at a 900 MHz center frequency, and the other at 1.8 GHz, both achieving the required phase noise spec and tuning range for the GSM and DCS-1800 system. The phase noise equals -108 dBc/Hz at 100 kHz offset for the 900 MHz version and -113 dBc/Hz at 200 kHz for the 1.8 GHz version. The power consumption is 9 and 11 mW. An eight-modulus prescaler operates together with both VCOs.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125922147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 106
An ATM application specific integrated processor 特定于ATM应用程序的集成处理器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606663
A. Harasawa, T. Kaganoi, T. Kanoh, H. Nishizaki, M. Suzuki, H. Tomizawa, T. Shindou
{"title":"An ATM application specific integrated processor","authors":"A. Harasawa, T. Kaganoi, T. Kanoh, H. Nishizaki, M. Suzuki, H. Tomizawa, T. Shindou","doi":"10.1109/CICC.1997.606663","DOIUrl":"https://doi.org/10.1109/CICC.1997.606663","url":null,"abstract":"An application specific integrated processor designed for ATM cell processing applications is described in this paper. A new dedicated architecture consisting of a custom-made CPU core, a pipeline input cell buffer and a content addressable memory (CAM) is employed to realize both high performance data processing and functional re-configurability. The chip has been implemented on 0.5 /spl mu/m CMOS. It consumes 2400 mW power under 3.3 V supply at 52 MHz clock frequency for a 155 Mbps high speed cell data stream. Programs for several different applications have been developed and are running on this chip. As a result of evaluation, each application program satisfies a required performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Efficient Monte-Carlo thermal noise simulation for /spl Sigma//spl Delta/ modulators /spl Sigma//spl Delta/调制器的高效蒙特卡罗热噪声模拟
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606676
Y. Dong, A. Opal
{"title":"Efficient Monte-Carlo thermal noise simulation for /spl Sigma//spl Delta/ modulators","authors":"Y. Dong, A. Opal","doi":"10.1109/CICC.1997.606676","DOIUrl":"https://doi.org/10.1109/CICC.1997.606676","url":null,"abstract":"This paper presents an efficient Monte-Carlo noise simulation method of /spl Sigma//spl Delta/ modulators in time domain. It can be used to simulate thermal noise, dithering and other noise effects. The simulation is at circuit level, where comparators, opamps, resistors, switches, capacitors and other linear elements are used as building blocks. This method has been implemented in SIMthermal, a simulator written in Fortran77. Three simulation examples are given.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125233475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1.9 GHz silicon receiver with on-chip image filtering 带有片上图像滤波的1.9 GHz硅接收器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606609
J. Macedo, M. Copeland, P. Schvan
{"title":"A 1.9 GHz silicon receiver with on-chip image filtering","authors":"J. Macedo, M. Copeland, P. Schvan","doi":"10.1109/CICC.1997.606609","DOIUrl":"https://doi.org/10.1109/CICC.1997.606609","url":null,"abstract":"A 1.9 GHz fully monolithic silicon superheterodyne front end receiver is presented; it consists of an LNA, a tunable image reject filter and a Gilbert cell mixer integrated in one die. The chip was fabricated using NORTEL's 0.5 micron bipolar technology with 25 GHz f/sub t/. The receiver was designed to operate with a 1.9 GHz RF and a 2.2 GHz L.O. For a 300 MHz IF. Measured performance for the complete receiver (packaged) was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3-28 dBm, 50 dB image rejection (tuned to reject a 2.5 GHz image frequency) and 15.9 mA current consumption at +3 V. The image rejection can be tuned from 2.4 GHz to 2.63 GHz. A new version with improved linearity is in fabrication.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125073668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Compact device modeling for circuit simulation 紧凑的器件建模电路仿真
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606604
C. McAndrew
{"title":"Compact device modeling for circuit simulation","authors":"C. McAndrew","doi":"10.1109/CICC.1997.606604","DOIUrl":"https://doi.org/10.1109/CICC.1997.606604","url":null,"abstract":"This paper reviews issues related to compact modeling for circuit simulation. The major emphasis is to detail common-sense guidelines for compact modeling and characterization that are not so common, and to highlight common numerical weaknesses and their solution. Aspects of high frequency modeling that are often overlooked are also addressed.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35 /spl mu/m CMOS technology for next-generation DSPs 采用0.35 /spl mu/m CMOS技术实现200 mhz 16/spl倍/16左至右无载乘子的VLSI实现下一代dsp
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606669
R. Kolagotla, H. Srinivas, G. Burns
{"title":"VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35 /spl mu/m CMOS technology for next-generation DSPs","authors":"R. Kolagotla, H. Srinivas, G. Burns","doi":"10.1109/CICC.1997.606669","DOIUrl":"https://doi.org/10.1109/CICC.1997.606669","url":null,"abstract":"We describe the VLSI implementation of a 16/spl times/16 left-to-right carry-free multiplier. Left-to-right multipliers are significantly faster than conventional right-to-left multipliers because they do not require a carry-propagate adder to complete the multiplication process. The key to the high speed of left-to-right multiplication is the fact that the most significant partial product digits are available in carry-save form earlier than they are in conventional right-to-left multipliers. Two conversion schemes for converting the most significant half of the partial products from carry-save to binary form are described. The first scheme uses a variation of the Ercegovac-Lang converter, and the second scheme uses a conventional carry-select adder. Experimental measurements are presented to show the feasibility of 200-MHz operation.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127906215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2 GHz balanced harmonic mixer for direct-conversion receivers 用于直接转换接收机的2ghz平衡谐波混频器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606612
T. Yamaji, H. Tanimoto
{"title":"A 2 GHz balanced harmonic mixer for direct-conversion receivers","authors":"T. Yamaji, H. Tanimoto","doi":"10.1109/CICC.1997.606612","DOIUrl":"https://doi.org/10.1109/CICC.1997.606612","url":null,"abstract":"To reduce DC offset caused by LO signal self-mixing in a direct-conversion receiver, a balanced harmonic mixer was proposed and fabricated by using a silicon bipolar technology. The measured self-mixing DC offset was equivalent to -92 dBm at the mixer input and is of the same order as equivalent input noise. This makes it possible to use a simple offset cancellation technique to overcome the self-mixing problem.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122424064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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