知识产权块的时序抽象

S. Venkatesh, R. Palermo, M. Mortazavi, K. Sakallah
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引用次数: 23

摘要

本文介绍了一种基于静态时序分析的大模块(> 5000个晶体管)时序模型的建立方法。该方法捕获块的传播延迟和其输出的转换率。更重要的是,它抽象了块的所有内部设置、保持和循环约束。由此产生的块计时模型可以用作块的时间行为的精确表示,从而避免了暴露块的内部实现的需要。块表征在知识产权封装和大型时间限制芯片的团队设计中得到应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Timing abstraction of intellectual property blocks
This paper describes a method for creating timing models of large blocks (>5,000 transistors) based on the use of static timing analysis. This method captures the block's propagation delays and the slew rates at its outputs. More importantly, it abstracts all the internal setup, hold, and loop constraints of the block. The resulting block timing model can thus be used as an accurate representation of the block's temporal behavior obviating the need for exposing the block's internal implementation. Block characterization finds application in intellectual property encapsulation and in team design of large timing-constrained chips.
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