VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35 /spl mu/m CMOS technology for next-generation DSPs

Abstract

We describe the VLSI implementation of a 16/spl times/16 left-to-right carry-free multiplier. Left-to-right multipliers are significantly faster than conventional right-to-left multipliers because they do not require a carry-propagate adder to complete the multiplication process. The key to the high speed of left-to-right multiplication is the fact that the most significant partial product digits are available in carry-save form earlier than they are in conventional right-to-left multipliers. Two conversion schemes for converting the most significant half of the partial products from carry-save to binary form are described. The first scheme uses a variation of the Ercegovac-Lang converter, and the second scheme uses a conventional carry-select adder. Experimental measurements are presented to show the feasibility of 200-MHz operation.