一种超低功耗CMOS电路的门级漏功率降低方法

J. P. Halter, Farid N. Najm
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引用次数: 291

摘要

为了降低CMOS产品的功耗,半导体厂商正在降低电源电压。这就要求晶体管的阈值电压也要降低,以保持足够的性能和噪声裕度。然而,这增加了p和n mosfet的亚阈值泄漏电流,这开始抵消从电源减少中获得的功率节省。随着阈值电压进一步降低,这个问题将在未来几代技术中恶化。为了克服这一点,我们提出了一种设计技术,可以在逻辑设计中使用,以减少泄漏电流和功率。我们的目标是在不使用时将电路部分置于“待机”模式的设计,这正在成为低功耗设计的常见方法。拟议的设计变更包括最小的开销电路,使电路进入“低漏待机状态”,无论何时进入待机状态,并允许它在重新激活时返回到原始状态。给出了一种计算低漏功率状态的有效算法。我们在ISCAS-89基准套件上演示了这种方法,并显示某些电路的泄漏功率降低高达54%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A gate-level leakage power reduction method for ultra-low-power CMOS circuits
In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in "standby" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.
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