A hardware/software partitioning technique with hierarchical design space exploration

Abstract

This paper describes a new hardware/software partitioning approach based on a new use of hierarchical modeling. A set of DSP examples are considered for codesign on a specific architecture in order to accelerate their performance on a target architecture including a standard DSP processor running concurrently with a custom SIMD processor. Through this set of examples, we demonstrate the effectiveness that such a use of hierarchy offers; mainly the extent of the design space explored during codesign and the acceleration of DSP algorithms on the target architecture.