Dynamic floating body control SOI CMOS circuits for power managed multimedia ULSIs

Abstract

A novel body potential controlling technique for floating SOI CMOS circuits is proposed and verified. High speed operation is realized with a small chip size by using body-floating SOI transistors. By using this technique, the threshold voltage of the body-floating transistors is varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced less than 1/10th compared to the non-control operation of the body potential and operates at high speed during the active period. There is no access penalty for the recovery operation from the standby mode. This technique supports sub 1 V operation, which is required for future battery operated devices with wide range covering.