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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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Integrated circuit technology options for RFIC's-present status and future directions RFIC集成电路技术选择的现状与未来方向
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606607
L. Larson
{"title":"Integrated circuit technology options for RFIC's-present status and future directions","authors":"L. Larson","doi":"10.1109/CICC.1997.606607","DOIUrl":"https://doi.org/10.1109/CICC.1997.606607","url":null,"abstract":"This paper summarizes the technology tradeoffs that are involved in the implementation of radiofrequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements-including noise-figure, linearity, gain, power dissipation. The advantages and disadvantages of each of the competing technologies-Si CMOS, and BJT, Si/SiGe HBTs, and GaAs MESFETs, PHEMTs and HBTs are examined.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 265
A sparse macromodeling method for RC interconnect multiports RC互连多端口稀疏宏建模方法
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606606
Y. Liu, L. Pileggi, A. Strojwas
{"title":"A sparse macromodeling method for RC interconnect multiports","authors":"Y. Liu, L. Pileggi, A. Strojwas","doi":"10.1109/CICC.1997.606606","DOIUrl":"https://doi.org/10.1109/CICC.1997.606606","url":null,"abstract":"This paper describes a technique for generating sparse RC interconnect macromodels. By inserting an artificial delay in the transconductance between distant port nodes, the technique can dramatically sparsify the time domain stencil of the N-port macromodel. The error introduced is measured in terms of the poles and residues of the RC circuit, thereby allowing accuracy vs. sparsity trade-offs to be made. Some examples are shown that demonstrate no noticeable loss of accuracy for significant improvements in sparsity.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power and compact desktop ATM PMD 一个低功耗和紧凑的桌面ATM PMD
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606641
Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii
{"title":"A low power and compact desktop ATM PMD","authors":"Y. Wakayama, F. Nakano, J. Takeuchi, N. Honda, K. Ishii, T. Sakamoto, T. Fujii","doi":"10.1109/CICC.1997.606641","DOIUrl":"https://doi.org/10.1109/CICC.1997.606641","url":null,"abstract":"A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 /spl mu/m CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm/sup 2/ are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123767173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-voltage 0.35 /spl mu/m CMOS/SOI technology for high-performance ASIC's 用于高性能ASIC的低电压0.35 /spl mu/m CMOS/SOI技术
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606659
A. Adan, T. Naka, S. Kaneko, D. Urabe, K. Higashi, A. Kagisawa
{"title":"Low-voltage 0.35 /spl mu/m CMOS/SOI technology for high-performance ASIC's","authors":"A. Adan, T. Naka, S. Kaneko, D. Urabe, K. Higashi, A. Kagisawa","doi":"10.1109/CICC.1997.606659","DOIUrl":"https://doi.org/10.1109/CICC.1997.606659","url":null,"abstract":"A 0.35 /spl mu/m CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126308069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability 一个5.1 ns, 5000门，CMOS PLD具有可选的倍频和系统内可编程性
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606686
J. Costello, J. Balicki, V. Bocchino, M. Chan, K. Nishiwaki, B. Nouban, N. Tran, B. Vest, M. Wong
{"title":"A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability","authors":"J. Costello, J. Balicki, V. Bocchino, M. Chan, K. Nishiwaki, B. Nouban, N. Tran, B. Vest, M. Wong","doi":"10.1109/CICC.1997.606686","DOIUrl":"https://doi.org/10.1109/CICC.1997.606686","url":null,"abstract":"A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126525449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel fully programmable switched-current IIR filter 一种新颖的全可编程开关电流IIR滤波器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606627
M. Omair Ahmad, Shenghong Wang
{"title":"A novel fully programmable switched-current IIR filter","authors":"M. Omair Ahmad, Shenghong Wang","doi":"10.1109/CICC.1997.606627","DOIUrl":"https://doi.org/10.1109/CICC.1997.606627","url":null,"abstract":"A fully programmable switched-current IIR filter using switched-current delay-multiplies units is described. The characteristics of the filter are fully programmable by simply changing the ratios of the coefficient transistors. To reduce the effect of non-ideal characteristics of MOS transistors, a high-performance differential switched-current memory cell is used as a basic building block. To reduce the chip area and maintain the required accuracy of the coefficients, an array consisting of three different sizes of transistors is designed instead of using a unit transistor array as coefficient transistors. A prototype second-order switched-current IIR filter array which consists of six second-order switched-current IIR filters has been fabricated with the standard 1.2 /spl mu/m CMOS process technology. Hard wiring technique is used for programming the filters. The test results show that the characteristics of the filters satisfy the design requirements.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A congestion-driven placement improvement algorithm for large scale sea-of-gates arrays 大规模栅极海阵列的拥塞驱动布局改进算法
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606692
T. Sadakane, H. Shirota, K. Takahashi, M. Terai, K. Okazaki
{"title":"A congestion-driven placement improvement algorithm for large scale sea-of-gates arrays","authors":"T. Sadakane, H. Shirota, K. Takahashi, M. Terai, K. Okazaki","doi":"10.1109/CICC.1997.606692","DOIUrl":"https://doi.org/10.1109/CICC.1997.606692","url":null,"abstract":"A fast placement improvement algorithm for large scale gate arrays is reported. This algorithm consists of a new cell padding phase and a fast iterative improvement phase. To reduce local routing congestion on a chip, the padding phase virtually expands the size of cells in the congested regions and relocates all the cells to eliminate the cell overlap, preserving the relative cell position. We have developed a formula by which to estimate from the expanded cell sizes the congestion after the relocation in each region on a chip. Using this, the padding phase determines cell sizes that will equalize the congestion throughout a chip, by simulated annealing. The iterative improvement phase minimizes the well known objective function that takes the local congestion into account, but our algorithm is faster because of the use of a new gain estimation method for determining a better position to which to move a cell. The experimental results on large gate array designs indicate that the routability of cell placement is considerably improved by our algorithm.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130561977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Full-chip harmonic balance 全片谐波平衡
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606651
D. Long, R. Melville, K. Ashby, B. Horton
{"title":"Full-chip harmonic balance","authors":"D. Long, R. Melville, K. Ashby, B. Horton","doi":"10.1109/CICC.1997.606651","DOIUrl":"https://doi.org/10.1109/CICC.1997.606651","url":null,"abstract":"Fast and accurate computation of the steady-state response of large nonlinear networks under periodic and quasi-periodic drive is a key simulation problem for integrated RF designs. In this paper we describe recent work which extends the method of Harmonic Balance to networks containing several million unknowns. A new implementation is described, which includes new methods of preconditioning linear solves and an efficient method of storing derivative information. Then we report simulation and bench measurement results for several large designs, including a complete dual-conversion transmitter chip with extracted layout parasitics.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
A BiCMOS double-low-IF receiver for GSM 用于GSM的BiCMOS双低中频接收机
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606680
M. Banu, H. Wang, M. Seidel, M. Tarsia, W. Fischer, J. Glas, A. Dec, V. Boccuzzi
{"title":"A BiCMOS double-low-IF receiver for GSM","authors":"M. Banu, H. Wang, M. Seidel, M. Tarsia, W. Fischer, J. Glas, A. Dec, V. Boccuzzi","doi":"10.1109/CICC.1997.606680","DOIUrl":"https://doi.org/10.1109/CICC.1997.606680","url":null,"abstract":"A new down-conversion technique for wireless terminals is proposed. The use of two IF stages at low frequencies eliminates the need for expensive SAW filters while avoiding some of the shortcomings of the direct conversion and single low-IF methods. High selectivity is realized with on-chip filters and inexpensive ceramic filters. A 0.5 /spl mu/m BiCMOS test chip demonstrates the principle via a GSM example.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115734886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core 一个4*2.5 Mchip/s直接序列扩频接收器，带有数字中频和集成ARM6内核
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606667
B. Gyselinckx, L. Rynders, M. Engels, I. Bolsens
{"title":"A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core","authors":"B. Gyselinckx, L. Rynders, M. Engels, I. Bolsens","doi":"10.1109/CICC.1997.606667","DOIUrl":"https://doi.org/10.1109/CICC.1997.606667","url":null,"abstract":"This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs digital IQ-downconversion of a carrier up to 10 MHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s. The receiver integrates an ARM6 core, memory, a UART, and flexible DSP hardware. Therefore, it is fully programmable. The use of macrocells and a self timed architecture allowed the design to have an aggressive design time of 7 months from specification to silicon. A low power redesign of the on-chip downconverter and decimator resulted in 45% power savings.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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