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Proceedings of CICC 97 - Custom Integrated Circuits Conference最新文献

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A 50 MHz 16-point FFT processor for WLAN applications 用于WLAN应用的50 MHz 16点FFT处理器
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606666
N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival
{"title":"A 50 MHz 16-point FFT processor for WLAN applications","authors":"N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival","doi":"10.1109/CICC.1997.606666","DOIUrl":"https://doi.org/10.1109/CICC.1997.606666","url":null,"abstract":"This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A field programmable analog array and its application 一种现场可编程模拟阵列及其应用
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606688
D. Anderson, C. Marcjan, D. Bersch, H. Anderson, P. Hu, O. Palusinski, D. Gettman, I. Macbeth, A. Bratt
{"title":"A field programmable analog array and its application","authors":"D. Anderson, C. Marcjan, D. Bersch, H. Anderson, P. Hu, O. Palusinski, D. Gettman, I. Macbeth, A. Bratt","doi":"10.1109/CICC.1997.606688","DOIUrl":"https://doi.org/10.1109/CICC.1997.606688","url":null,"abstract":"A Field Programmable Analog Array (FPAA) is presented based on switched capacitor technology. The architecture offers an unconstrained topology similar to its digital counterpart, containing an array of identical undedicated analog cells. This makes it possible to program both the functionality of each cell and the interconnect between cells. As a result a large number of diverse architectures may be implemented. The analog array can be programmed to perform many of the routine tasks associated with control systems design. Its linear and non-linear signal processing abilities can provide a wide range of waveform generation functions. The device can also be programmed for precise phase and magnitude characteristics. Some examples related to control systems are discussed.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126237949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
High-level area prediction for power estimation 用于功率估计的高级区域预测
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606672
M. Nemani, Farid N. Najm
{"title":"High-level area prediction for power estimation","authors":"M. Nemani, Farid N. Najm","doi":"10.1109/CICC.1997.606672","DOIUrl":"https://doi.org/10.1109/CICC.1997.606672","url":null,"abstract":"High-level power estimation, when given only a high level design specification such as a functional or RTL description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model that makes use of a new complexity measure. The model is empirical, and is based on an observed relationship between the proposed complexity measure, which is easily measurable using Monte-Carlo simulation, and its optimal implementation (gate-count). This model has been implemented, and empirical results demonstrating its feasibility and utility are presented.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127544179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fully integrated LVD clock generation/distribution IC 完全集成的LVD时钟生成/分配IC
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606584
Roger Emeigh, J. Strom
{"title":"Fully integrated LVD clock generation/distribution IC","authors":"Roger Emeigh, J. Strom","doi":"10.1109/CICC.1997.606584","DOIUrl":"https://doi.org/10.1109/CICC.1997.606584","url":null,"abstract":"This paper describes a clock generation and distribution IC, The design contains a fully differential PLL with a 1 GHz VCO and programmable dividers to form a frequency synthesizer with two synchronous output frequencies from 7.7 MHz to 500 MHz. LVD, low voltage differential, output drivers provide 12 low skew copies of the synthesized frequency with on chip termination. The module can be used as either a frequency synthesizer and distributor or as a distributor alone. The design obtains +/-20 ps cycle-cycle jitter, 40 ps driver-driver skew and 180 ps chip to chip skew. The fully integrated design is implemented on a 2.85 mm by 3.3 mm chip in a 3.3 V, 0.45 um L/sub eff/ BiCMOS technology with 12 GHz f/sub t/ npn's and is packaged in a 68 pin PLCC.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI implementation of single chip encoder/decoder for low bitrate visual communication 用于低比特率视觉通信的单片编/解码器的VLSI实现
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606618
Koji Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa
{"title":"VLSI implementation of single chip encoder/decoder for low bitrate visual communication","authors":"Koji Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa","doi":"10.1109/CICC.1997.606618","DOIUrl":"https://doi.org/10.1109/CICC.1997.606618","url":null,"abstract":"A single chip encoder and decoder dedicated to the low bitrate visual communication is described, with the main theme focused on the object extraction and vector quantization. A new scheme is devised for a detailed edge detector, which is to seek horizontal and vertical edges simultaneously. A new concept is also introduced into a PE (Processing Element) array so as to be commonly used by the vector quantizer and the motion estimator. Owing to a sophisticated architecture, these CODEC facilities have been implemented in 72.24 mm/sup 2/ by a 0.6 /spl mu/m triple-metal CMOS technology, which can enable the visual communication of QCIF (176/spl times/144) 10 fps pictures at a bitrate below 30 K bps. The designed encoder and decoder operate at 10.0 MHz, and dissipate 147 mW from a single 3.3 V supply.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124063628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 250 MHz dual port cursor RAM using dynamic data alignment architecture 250mhz双端口游标RAM，采用动态数据对齐架构
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606628
Y. Nakase, H. Kono, T. Tokuda
{"title":"A 250 MHz dual port cursor RAM using dynamic data alignment architecture","authors":"Y. Nakase, H. Kono, T. Tokuda","doi":"10.1109/CICC.1997.606628","DOIUrl":"https://doi.org/10.1109/CICC.1997.606628","url":null,"abstract":"This paper describes a dual port cursor RAM operating in real time. Cursor RAMs have been composed of two memory planes. The pixel port requires data from both planes at the same time. However, this has not been realized so far because each port defines its address space differently. A dynamic data alignment architecture coordinates these different requests. This architecture reduces a large amount of control circuits and makes it possible to operate in real time. The RAM is fabricated in a double metal 0.5 /spl mu/m CMOS process technology. The active area is 1.5/spl times/1.6 mm including a couple of shift registers. It operates up to 263 MHz at the supply voltage of 3.3 V.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quick placement with geometric constraints 快速放置几何约束
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606689
E. Malavasi, J. L. Ganley, E. Charbon
{"title":"Quick placement with geometric constraints","authors":"E. Malavasi, J. L. Ganley, E. Charbon","doi":"10.1109/CICC.1997.606689","DOIUrl":"https://doi.org/10.1109/CICC.1997.606689","url":null,"abstract":"In this paper an original constraint-driven placement tool targeted at full-custom mixed-signal design is described. One of its main objectives is to quickly obtain feasible layout configurations, and explore efficiently the effect of different sets of constraints in an interactive environment. By using direct-approach algorithms, all feasible constraints are met by construction. Overconstraints are detected, and quick feedback is given to the user about infeasible requirements. Good results have been obtained on a significant set of industrial-strength test cases.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127071005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1.5-V 3-mW 10-bit 50-Ms/s CMOS DAC with low distortion and low intermodulation in standard digital CMOS process 一种标准数字CMOS工艺中具有低失真、低互调的1.5 v 3 mw 10位50毫秒/秒CMOS DAC
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606697
N. Tan
{"title":"A 1.5-V 3-mW 10-bit 50-Ms/s CMOS DAC with low distortion and low intermodulation in standard digital CMOS process","authors":"N. Tan","doi":"10.1109/CICC.1997.606697","DOIUrl":"https://doi.org/10.1109/CICC.1997.606697","url":null,"abstract":"For telecommunication applications, the dynamic performance of a digital-to-analog converter such as intermodulation and spurious-free dynamic range is of the greatest importance and the static performance is of minor concern. This paper presents the design of a 1.5 V 10-bit CMOS digital-to-analog converter in a 0.6 /spl mu/m digital CMOS process for telecommunication applications. It features an intermodulation level less than -60 dBc at 10 Ms/s and -55 dBc at 50 Ms/s, and a spurious-free dynamic range of 59 dB at 10 Ms/s and 48 dB at 50 Ms/s. The power dissipation is about 1.5 mW at 10 Ms/s and about 3 mW at 50 Ms/s.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications 一种用于磁场无线应用的微功率CMOS，直接转换，VLF接收器芯片
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606657
D. Binkley, J. M. Rochelle, B. K. Swann, L. Clonts, R. N. Goble
{"title":"A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications","authors":"D. Binkley, J. M. Rochelle, B. K. Swann, L. Clonts, R. N. Goble","doi":"10.1109/CICC.1997.606657","DOIUrl":"https://doi.org/10.1109/CICC.1997.606657","url":null,"abstract":"A micropower CMOS, direct-conversion VLF receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, PLL-synthesized receiver covers a frequency range of 10-100 kHz and provides both analog and digital 9-bit I and Q baseband outputs. Lateral bipolar transistors are utilized for low flicker noise and low DC offsets, and special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 /spl mu/V noise floor, 300 Hz BW). The 100% duty-cycle receiver, intended for long-battery life wireless applications, operates at 360 /spl mu/W from a 6-V battery.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114636269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A novel mixed signal programmable device with on-chip microprocessor 一种新型片上微处理器混合信号可编程器件
Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI: 10.1109/CICC.1997.606594
J. Faura, C. Horton, P. van Duong, J. Madrenas, M. Aguirre, J. M. Inserser
{"title":"A novel mixed signal programmable device with on-chip microprocessor","authors":"J. Faura, C. Horton, P. van Duong, J. Madrenas, M. Aguirre, J. M. Inserser","doi":"10.1109/CICC.1997.606594","DOIUrl":"https://doi.org/10.1109/CICC.1997.606594","url":null,"abstract":"In this paper we present a novel field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog signals. The device is especially suitable for development and fast prototyping of mixed signal integrated applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"30 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124533786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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