A 250 MHz dual port cursor RAM using dynamic data alignment architecture

This paper describes a dual port cursor RAM operating in real time. Cursor RAMs have been composed of two memory planes. The pixel port requires data from both planes at the same time. However, this has not been realized so far because each port defines its address space differently. A dynamic data alignment architecture coordinates these different requests. This architecture reduces a large amount of control circuits and makes it possible to operate in real time. The RAM is fabricated in a double metal 0.5 /spl mu/m CMOS process technology. The active area is 1.5/spl times/1.6 mm including a couple of shift registers. It operates up to 263 MHz at the supply voltage of 3.3 V.