VLSI implementation of single chip encoder/decoder for low bitrate visual communication

Abstract

A single chip encoder and decoder dedicated to the low bitrate visual communication is described, with the main theme focused on the object extraction and vector quantization. A new scheme is devised for a detailed edge detector, which is to seek horizontal and vertical edges simultaneously. A new concept is also introduced into a PE (Processing Element) array so as to be commonly used by the vector quantizer and the motion estimator. Owing to a sophisticated architecture, these CODEC facilities have been implemented in 72.24 mm/sup 2/ by a 0.6 /spl mu/m triple-metal CMOS technology, which can enable the visual communication of QCIF (176/spl times/144) 10 fps pictures at a bitrate below 30 K bps. The designed encoder and decoder operate at 10.0 MHz, and dissipate 147 mW from a single 3.3 V supply.