一个5.1 ns, 5000门，CMOS PLD具有可选的倍频和系统内可编程性

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606686

J. Costello, J. Balicki, V. Bocchino, M. Chan, K. Nishiwaki, B. Nouban, N. Tran, B. Vest, M. Wong

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引用次数: 0

摘要

介绍了一种高密度可编程逻辑器件(PLD)，该器件专为高性能和易于在生产流程中使用而开发。该器件采用0.5 /spl mu/m的三层金属工艺设计，可产生55 kmil/sup / 2/的芯片尺寸，并具有内置的倍频器，可实现高达140 MHz的系统性能。

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A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability

A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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