Low-voltage 0.35 /spl mu/m CMOS/SOI technology for high-performance ASIC's

Abstract

A 0.35 /spl mu/m CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology.