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A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback 通过DSCR反馈降低时钟抖动灵敏度的连续时间ΔΣ调制器
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126701
D. Radjen, P. Andreani, Martin Anderson, Lars Sundström
{"title":"A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback","authors":"D. Radjen, P. Andreani, Martin Anderson, Lars Sundström","doi":"10.1109/NORCHP.2011.6126701","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126701","url":null,"abstract":"This paper presents a low-power multi-bit continuous-time ΔΣ modulator with a new approach to clock jitter reduction utilizing switched-capacitor-resistor techniques. The modulator features a 3rd order loop filter, implemented with active RC integrators, and 3-bit quantizer and feedback DACs. The ΔΣ modulator has been implemented in a 65nm CMOS process and tested. It achieves a peak SNDR of 70 dB in a 125 kHz signal bandwidth while consuming 380 µW. The combination of a high-order loop filter and multi-bit quantizer allows for a high resolution at a low sampling frequency of 4MHz, corresponding to an oversampling ratio of 16.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A linearized 1.6–5 GHz low noise amplifier using positive feedback in 65 nm CMOS 采用65纳米CMOS的正反馈线性化1.6-5 GHz低噪声放大器
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126738
Anders Nejdel, Markus Törmänen, H. Sjöland
{"title":"A linearized 1.6–5 GHz low noise amplifier using positive feedback in 65 nm CMOS","authors":"Anders Nejdel, Markus Törmänen, H. Sjöland","doi":"10.1109/NORCHP.2011.6126738","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126738","url":null,"abstract":"A 1.6–5 GHz low noise amplifier has been designed and simulated in a 65 nm CMOS process. The linearity is increased by employing positive feedback using transistors biased in the sub-threshold region. Simulations show that mismatches in the circuit can be neutralized by adjusting the bias point of the feedback transistors. The amplifier has a noise figure below 3 dB, a third order intercept point of +10 dBm, and a voltage gain above 23 dB. In order to obtain a flat gain the amplifier uses a resistive load in combination with current bleeding transistors which give a noise cancelling effect. The circuit consumes 4.9 mA from a 1.5 V supply.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133453316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A digital PLL with a multi-delay coarse-fine TDC 具有多延迟粗-细TDC的数字锁相环
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126745
Ying Wu, P. Lu, P. Andreani
{"title":"A digital PLL with a multi-delay coarse-fine TDC","authors":"Ying Wu, P. Lu, P. Andreani","doi":"10.1109/NORCHP.2011.6126745","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126745","url":null,"abstract":"A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implemented. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is −125 and −151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs 四阶增量稳定性的实证研究-ΣΔ-ADCs
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126713
Johannes Uhlig, R. Schüffny
{"title":"An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs","authors":"Johannes Uhlig, R. Schüffny","doi":"10.1109/NORCHP.2011.6126713","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126713","url":null,"abstract":"In order to find relationships between Noise-Transfer-Function (NTF) characteristics and stability of a Incremental-Delta-Sigma ADC (I-DS-ADC) 40.000 different NTF has been investigated. A fast and easy to use criterion to determine, if an NTF of an I-DS-ADC of 4th-order is likely to be stable was found. The novel criterion is fast and easy to use and covers a much bigger variety of possible NTFs compared to recent criteria.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Model-based rapid prototyping of multirate digital signal processing algorithms 基于模型的多速率数字信号处理算法快速原型
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126736
S. Butt, L. Lavagno
{"title":"Model-based rapid prototyping of multirate digital signal processing algorithms","authors":"S. Butt, L. Lavagno","doi":"10.1109/NORCHP.2011.6126736","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126736","url":null,"abstract":"In this paper we present a design methodology that can be used for rapid prototyping and implementation of multi-rate digital signal processing algorithms. We start from a verified Simulink model of a digital down convertor and then proceed through model refinement, code generation, block interface definition and synthesis steps for FPGA prototyping and implementation. At the end we report FPGA implementation results and compare these results with the results obtained from another model based design tool, namely HDL Coder.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124883835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Contention aware scheduling for NoC-based real-time systems 基于noc的实时系统的竞争感知调度
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126723
Mihkel Tagel, P. Ellervee, T. Hollstein, G. Jervan
{"title":"Contention aware scheduling for NoC-based real-time systems","authors":"Mihkel Tagel, P. Ellervee, T. Hollstein, G. Jervan","doi":"10.1109/NORCHP.2011.6126723","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126723","url":null,"abstract":"This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip (NoC). Due to the communication complexity of such systems it is difficult to estimate the communication delay, making implementation of real-time systems on NoCs virtually impossible. In this work we propose a method for simple and efficient communication modelling and synthesis for dynamically reconfigurable NoC-based systems that enables contention aware scheduling. The network model is refined such that produced schedules can be verified with a cycle-accurate simulator.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers 时变与非时变Volterra分析在混频器畸变贡献分析中的比较
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126715
T. Rahkonen, J. Aikio, J. Hamina
{"title":"Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers","authors":"T. Rahkonen, J. Aikio, J. Hamina","doi":"10.1109/NORCHP.2011.6126715","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126715","url":null,"abstract":"The conversion gain in mixers is traditionally calculated using a time-varying (TV) gain model and small signal excitation. In this paper we compare this approach with a brute force expansion of a polynomial model with multitone input. It is seen that the polynomial expansion preserves more information, and shows some distortion products that the time-varying model ignores. The polynomial expansion is used in Volterra-on-Harmonic Balance distortion contribution analysis to analyse both mixing and amplifying circuits.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132386062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature dependent wire delay estimation in floorplanning 地板规划中与温度相关的导线延迟估计
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126741
Andreas Thor Winther, Wei Liu, A. Nannarelli, S. Vrudhula
{"title":"Temperature dependent wire delay estimation in floorplanning","authors":"Andreas Thor Winther, Wei Liu, A. Nannarelli, S. Vrudhula","doi":"10.1109/NORCHP.2011.6126741","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126741","url":null,"abstract":"Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment results show that a shorter delay can be achieved using the proposed method. In addition, we also discuss the congestion and reliability issues as they are closely related to routing and temperature.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132292643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL 基于亚阈值SCL的系统自适应错误检测时序电路的测量
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126746
M. Turnquist, E. Laulainen, Jani Mäkipää, L. Koskinen
{"title":"Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL","authors":"M. Turnquist, E. Laulainen, Jani Mäkipää, L. Koskinen","doi":"10.1109/NORCHP.2011.6126746","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126746","url":null,"abstract":"Timing error detection (TED) microprocessors are able to eliminate large timing margins by operating up to a voltage-frequency point in which intermittent errors occur. The detection of these errors requires an error-detection sequential (EDS) circuit. This paper presents the measurements of an EDS circuit called TEDsc. Using subthreshold source-coupled logic, TEDsc is able to dynamically adapt to system-level requirements. Measurements of TEDsc are presented in terms of a new system-level TED definition. TEDsc is implemented in 65 nm CMOS, has an area of 97.5 µm2, and consumes 79 pW (Vdd=250 mV). TEDsc operates at a clock period (TCLK) of 150 F04 at Vdd=400 mV with a sufficiently large detection window. By decreasing the size of the detection window, TEDsc can operate to at least TCLK=50 F04.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120865340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip 一种用于容错片上网络的低成本处理元件恢复机制
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126734
Khalid Latif, A. Rahmani, T. Seceleanu, H. Tenhunen
{"title":"A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip","authors":"Khalid Latif, A. Rahmani, T. Seceleanu, H. Tenhunen","doi":"10.1109/NORCHP.2011.6126734","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126734","url":null,"abstract":"A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121664399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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