A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback

Abstract

This paper presents a low-power multi-bit continuous-time ΔΣ modulator with a new approach to clock jitter reduction utilizing switched-capacitor-resistor techniques. The modulator features a 3rd order loop filter, implemented with active RC integrators, and 3-bit quantizer and feedback DACs. The ΔΣ modulator has been implemented in a 65nm CMOS process and tested. It achieves a peak SNDR of 70 dB in a 125 kHz signal bandwidth while consuming 380 µW. The combination of a high-order loop filter and multi-bit quantizer allows for a high resolution at a low sampling frequency of 4MHz, corresponding to an oversampling ratio of 16.