{"title":"基于模型的多速率数字信号处理算法快速原型","authors":"S. Butt, L. Lavagno","doi":"10.1109/NORCHP.2011.6126736","DOIUrl":null,"url":null,"abstract":"In this paper we present a design methodology that can be used for rapid prototyping and implementation of multi-rate digital signal processing algorithms. We start from a verified Simulink model of a digital down convertor and then proceed through model refinement, code generation, block interface definition and synthesis steps for FPGA prototyping and implementation. At the end we report FPGA implementation results and compare these results with the results obtained from another model based design tool, namely HDL Coder.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Model-based rapid prototyping of multirate digital signal processing algorithms\",\"authors\":\"S. Butt, L. Lavagno\",\"doi\":\"10.1109/NORCHP.2011.6126736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a design methodology that can be used for rapid prototyping and implementation of multi-rate digital signal processing algorithms. We start from a verified Simulink model of a digital down convertor and then proceed through model refinement, code generation, block interface definition and synthesis steps for FPGA prototyping and implementation. At the end we report FPGA implementation results and compare these results with the results obtained from another model based design tool, namely HDL Coder.\",\"PeriodicalId\":108291,\"journal\":{\"name\":\"2011 NORCHIP\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 NORCHIP\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2011.6126736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2011.6126736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Model-based rapid prototyping of multirate digital signal processing algorithms
In this paper we present a design methodology that can be used for rapid prototyping and implementation of multi-rate digital signal processing algorithms. We start from a verified Simulink model of a digital down convertor and then proceed through model refinement, code generation, block interface definition and synthesis steps for FPGA prototyping and implementation. At the end we report FPGA implementation results and compare these results with the results obtained from another model based design tool, namely HDL Coder.