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2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/vlsicircuits52068.2021.9492342
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引用次数: 0
A 47.5nJ Resistor-to-Digital Converter for Detecting BTEX with 0.06ppb-Resolution 用于0.06ppb分辨率BTEX检测的47.5nJ电阻-数字转换器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492408
Yongtae Lee, Byeonghwa Cho, Changuk Lee, Jongbaeg Kim, Youngcheol Chae
{"title":"A 47.5nJ Resistor-to-Digital Converter for Detecting BTEX with 0.06ppb-Resolution","authors":"Yongtae Lee, Byeonghwa Cho, Changuk Lee, Jongbaeg Kim, Youngcheol Chae","doi":"10.23919/VLSICircuits52068.2021.9492408","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492408","url":null,"abstract":"This paper describes an energy-efficient resistor-to-digital converter (RDC) for detecting benzene, toluene, ethylbenzene and xylene (BTEX). The sensor’s selectivity is adjusted by the different heat levels, thereby detecting the BTEX with a single-R sensor. The sensor is directly digitized by an energy-efficient RDC based on a continuous-time delta-sigma ADC. The proposed RDC achieves a better energy-efficiency by processing the signal in current domain. The prototype chip implemented in a 0.11-µm CMOS consumes only 95µW from a 1.5-V supply. It achieves a resistance resolution of 863mΩ with a 0.5-ms measurement time. This corresponds to a gas resolution of 0.06ppb and an energy per measurement of 47.5nJ. This work is fully verified through the BTEX measurements.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.4-6 GHz Receiver for LTE and WiFi 用于LTE和WiFi的0.4-6 GHz接收器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492422
Hossein Razavi, B. Razavi
{"title":"A 0.4-6 GHz Receiver for LTE and WiFi","authors":"Hossein Razavi, B. Razavi","doi":"10.23919/VLSICircuits52068.2021.9492422","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492422","url":null,"abstract":"A universal receiver employs a feedback method to alleviate noise-linearity trade-offs and a new harmonic rejection (HR) method that does not require accurate phase matching. Realized in 28-nm CMOS technology, the prototype provides channel selection filtering at RF for channel bandwidths from 200 kHz to 160 MHz and exhibits a noise figure of 2.1-4.2 dB with HR > 60.8 dB while drawing 49 mW.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery 60gb /s 1.2 pj /bit 1/4速率PAM4接收机，带- 8db JTRAN 40mhz 0.2 uipp JTOL时钟和数据恢复
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492377
Li Wang, Zhao Zhang, C. Yue
{"title":"A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery","authors":"Li Wang, Zhao Zhang, C. Yue","doi":"10.23919/VLSICircuits52068.2021.9492377","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492377","url":null,"abstract":"This paper presents a source-synchronous 60-Gb/s quarter-rate (1/4-rate) PAM4 receiver (Rx) with a jitter compensation clock and data recovery circuit (JCCDR) to overcome the stringent trade-off between jitter transfer (JTRAN) and jitter tolerance bandwidth (JTOL BW). The jitter compensation circuit (JCC) utilizes the delay-locked loop (DLL) filter voltage to produce a complementary control signal VLFINV, which modulates a group of complementary voltage-controlled delay lines (C-VCDL) so to negate the JTRANs on the recovered data and clock signals. The proposed 40-nm CMOS Rx test chip achieves error-free operation with PAM4 input from 30 to 60 Gb/s. The JCCDR achieves a 40-MHz JTOL BW with over 0.2-UIPP jitter amplitude while maintaining a -8-dB JTRAN. A jitter compensation ratio of around 60% has been achieved up to 40 MHz.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur 一种3.3 ghz 4.6 mw分数- n型ii型混合开关电容采样锁相环，采用嵌入式cdac数字积分路径，参考杂散为- 80 dbc
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492381
Zule Xu, Masaru Osada, T. Iizuka
{"title":"A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur","authors":"Zule Xu, Masaru Osada, T. Iizuka","doi":"10.23919/VLSICircuits52068.2021.9492381","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492381","url":null,"abstract":"We present a type-II fractional-N hybrid switched-capacitor sampling PLL, using a capacitive digital-to-analog converter (CDAC) as a sampler and an analog adder receiving the digital integrator’s output. To guarantee sufficient CDAC settling time and filter switch-on time, we designed a synchronous timing generator utilizing the multi-modulus divider’s (MMDIV’s) inter-stage clocks. The prototype chip in 65-nm CMOS achieves −80-dBc reference spur, 236-fs integrated RMS jitter, and 4.6-mW power consumption, translating to −246-dB FoM.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125451726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge 在边缘完成端到端面部分析的亚毫瓦双引擎机器学习推理片上系统
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492401
Petar Jokic, E. Azarkhish, Régis Cattenoz, Engin Türetken, L. Benini, S. Emery
{"title":"A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge","authors":"Petar Jokic, E. Azarkhish, Régis Cattenoz, Engin Türetken, L. Benini, S. Emery","doi":"10.23919/VLSICircuits52068.2021.9492401","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492401","url":null,"abstract":"Smart vision-based IoT applications operate on a sub-mW power budget while requiring power-hungry always-on image processing capabilities. This work presents a system-on-chip (SoC) that enables hierarchical processing of face analysis under multiple sub-mW operating scenarios using two tightly coupled machine learning (ML) accelerators. A dynamically scalable binary decision tree (BDT) engine for face detection (FD) allows triggering a multi-precision convolutional neural network (CNN) engine for subsequent face recognition (FR). The 22nm SoC can therefore dynamically trade-off image analysis depth, frames-per-second (FPS), accuracy, and power consumption. It implements complete end-to-end edge processing, enabling always-on FD and FR within the tight 1mW power budget of a 55mm diameter indoor solar panel. The SoC achieves >2x improvement in energy efficiency at iso-accuracy and iso-FPS over state-of-the-art (SoA) systems.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114459324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
OTA-free 1-1 MASH ADC using Fully Passive Noise Shaping SAR & VCO ADC 采用全无源噪声整形SAR和VCO ADC的无ota 1-1 MASH ADC
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492344
S. T. Chandrasekaran, S. Bhanushali, S. Pietri, A. Sanyal
{"title":"OTA-free 1-1 MASH ADC using Fully Passive Noise Shaping SAR & VCO ADC","authors":"S. T. Chandrasekaran, S. Bhanushali, S. Pietri, A. Sanyal","doi":"10.23919/VLSICircuits52068.2021.9492344","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492344","url":null,"abstract":"We present an OTA-free 1-1 MASH ADC utilizing a fully passive noise shaping (FPNS) SAR as first-stage and open-loop VCO ADC as second stage. The key contribution of this work is to address the challenge of driving large sampling capacitor for high resolution NS-SAR. The proposed architecture reduces resolution of SAR stage and leverages residue attenuation due to passive charge sharing in the FPNS SAR to linearize the VCO. Combining an FPNS SAR with a VCO ADC shapes in-band thermal noise of VCO and SAR comparator at ADC output. Additionally, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16mW while achieving an SNDR/DR of 71.5/75.8dB over a 1.1MHz bandwidth and walden FoM of 23.3fJ/step which is the lowest in 65nm technology.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126812996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation 具有隐式冗余推测和批归一化重构的28nm 276.55TFLOPS/W稀疏深度神经网络训练处理器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492420
Yang Wang, Yubin Qin, Dazheng Deng, Ji-de Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, S. Yin
{"title":"A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation","authors":"Yang Wang, Yubin Qin, Dazheng Deng, Ji-de Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, S. Yin","doi":"10.23919/VLSICircuits52068.2021.9492420","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492420","url":null,"abstract":"A dynamic weight pruning (DWP) explored processor, named Trainer, is proposed for energy-efficient deep-neural-network (DNN) training on edge-device. It has three key features: 1) A implicit redundancy speculation unit (IRSU) improves 1.46× throughput. 2) A dataflow, allowing a reuse-adaptive dynamic compression and PE regrouping, increases 1.52× utilization. 3) A data-retrieval eliminated batch-normalization (BN) unit (REBU) saves 37.1% of energy. Trainer achieves a peak energy efficiency of 276.55TFLOPS/W. It reduces 2.23× training energy and offers a 1.76× training speedup compared with the state-of-the-art sparse DNN training processor.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator 基于电荷补偿调节器的3D NAND闪存节能升压系统
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492355
H. Jeong, Seonghwan Cho
{"title":"An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator","authors":"H. Jeong, Seonghwan Cho","doi":"10.23919/VLSICircuits52068.2021.9492355","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492355","url":null,"abstract":"This paper presents an energy-efficient wordline driver for a triple level cell 3D NAND flash. Unlike conventional circuit that has a large charge pump and high-voltage regulators operating under the inefficient stepped-up voltage, the proposed circuit has a distributed charge pump (CP) that directly drive the wordlines, aided by a charge compensating regulator that operate under the nominal supply and produces a ripple free output. The proposed voltage driver for a 39 wordline layer is fabricated in 180nm UHV process and it consumes 99.8nJ from a 2.2V during 1 unit of program pulse and verify period, which is more than 2.1x improvement in energy efficiency compared to the conventional scheme.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130105385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
All-Directional Dual Pixel Auto Focus Technology in CMOS Image Sensors CMOS图像传感器的全方位双像素自动对焦技术
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492472
E. Shim, Kyungho Lee, J. Pyo, Wooseok Choi, Jungbin Yun, T. Jung, Kyungduck Lee, Seyoung Kim, Chanhee Lee, Seungki Baek, Hyuncheol Kim, Sungsoo Choi, Junseok Yang, Kyoungmok Son, Jongwon Choi, Howoo Park, Bumsuk Kim, JungChak Ahn, Duckhyun Chang
{"title":"All-Directional Dual Pixel Auto Focus Technology in CMOS Image Sensors","authors":"E. Shim, Kyungho Lee, J. Pyo, Wooseok Choi, Jungbin Yun, T. Jung, Kyungduck Lee, Seyoung Kim, Chanhee Lee, Seungki Baek, Hyuncheol Kim, Sungsoo Choi, Junseok Yang, Kyoungmok Son, Jongwon Choi, Howoo Park, Bumsuk Kim, JungChak Ahn, Duckhyun Chang","doi":"10.23919/VLSICircuits52068.2021.9492472","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492472","url":null,"abstract":"We developed a dual pixel with accurate and all-directional auto focus (AF) performance in CMOS image sensor (CIS). The optimized in-pixel deep trench isolation (DTI) provided accurate AF data and good image quality in the entire image area and over whole visible wavelength range. Furthermore, the horizontal-vertical (HV) dual pixel with the slanted in-pixel DTI enabled the acquisition of all-directional AF information by the conventional dual pixel readout method. These technologies were demonstrated in 1.4μm dual pixel and will be applied to the further shrunken pixels.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127463555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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