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2021 Symposium on VLSI Circuits最新文献

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All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP 全数字闭环统一保持/唤醒钳在10nm 4核x86 IP
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492376
C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. Tschanz, M. Khellah
{"title":"All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP","authors":"C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. Tschanz, M. Khellah","doi":"10.23919/VLSICircuits52068.2021.9492376","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492376","url":null,"abstract":"A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (VRETENTION) is presented. All-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33%/28% for core/IP, with 120ns wake up latency while addressing impact of PVT variations.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab 在CMOS晶圆厂集成的石墨烯电吸收调制器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492495
Cheng-Han Wu, S. Brems, D. Yudistira, D. Cott, A. Milenin, K. Vandersmissen, A. Maestre, A. Centeno, J. Campenhout, C. Huyghebaert, M. Pantouvaki
{"title":"Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab","authors":"Cheng-Han Wu, S. Brems, D. Yudistira, D. Cott, A. Milenin, K. Vandersmissen, A. Maestre, A. Centeno, J. Campenhout, C. Huyghebaert, M. Pantouvaki","doi":"10.23919/VLSICircuits52068.2021.9492495","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492495","url":null,"abstract":"We demonstrate graphene electro-absorption modulators (EAM) integrated on 300mm wafers. The integration is based on imec’s 300mm silicon photonics platform and the full integration sequence is using standard CMOS production tools expect for the 6-inch CVD graphene growth and transfer, transferred by Graphenea. 164x TE EAMs were measured per wafer and demonstrate 90% yield with modulation efficiency (ME) of 41±5.6 dB/mm for 8V voltage swing, after process optimization. The 3dB bandwidth of the EAMs is 14.9±1.2 GHz for the device with 50µm active length. Both parameters show comparable performance with lab-based devices, obtained on coupons using similar CVD graphene. This work paves the way to enable high-volume manufacturing of 2D-material-based photonics devices.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125455079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
106 Gb/s PAM-4 Transmitter With 2.1 Vppd Swing in 7nm FinFET Process 106gb /s PAM-4发射机，7nm FinFET工艺，2.1 Vppd摆幅
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492349
H. Sepehrian, Stephen Alie, P. Madeira, D. Tonietto
{"title":"106 Gb/s PAM-4 Transmitter With 2.1 Vppd Swing in 7nm FinFET Process","authors":"H. Sepehrian, Stephen Alie, P. Madeira, D. Tonietto","doi":"10.23919/VLSICircuits52068.2021.9492349","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492349","url":null,"abstract":"This paper demonstrates a high swing 106Gb/s PAM-4 transmitter in 7nm FinFET process. The 7-bit DAC based transmitter is designed to directly drive a range of TOSAs in either single ended or differential configuration eliminating the cost and power of an additional laser driver IC. Using a 2.4V supply, it achieves 2.1Vpp differential and 1.05Vpp single-ended swing across a 50Ω load. Total power consumption of the transmitter was found to be 2.63 pJ/bit with 2.4V supply and 2.23 pJ/b with 1.5 V supply and external bias-T.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128192761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Photon-Counting 4Mpixel Stacked BSI Quanta Image Sensor with 0.3e- Read Noise and 100dB Single-Exposure Dynamic Range 具有0.3e-读噪声和100dB单曝光动态范围的光子计数400万像素堆叠BSI量子图像传感器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492410
Jiaju Ma, Dexue Zhang, Omar A. Elgendy, S. Masoodian
{"title":"A Photon-Counting 4Mpixel Stacked BSI Quanta Image Sensor with 0.3e- Read Noise and 100dB Single-Exposure Dynamic Range","authors":"Jiaju Ma, Dexue Zhang, Omar A. Elgendy, S. Masoodian","doi":"10.23919/VLSICircuits52068.2021.9492410","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492410","url":null,"abstract":"This paper reports a 4Mpixel, 3D-stacked backside illuminated Quanta Image Sensor (QIS) with 2.2um pixels that can operate simultaneously in photon-counting mode with deep sub-electron read noise (0.3e- rms) and linear integration mode with large full-well capacity (30k e-). A single-exposure dynamic range of 100dB is realized with this dual-mode readout under room temperature. This QIS device uses a cluster-parallel readout architecture to achieve up to 120fps frame rate at 550mW power consumption.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 27-73 GHz Injection-Locked Frequency Divider 一种27-73 GHz注入锁定分频器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492457
Hossein Razavi, B. Razavi
{"title":"A 27-73 GHz Injection-Locked Frequency Divider","authors":"Hossein Razavi, B. Razavi","doi":"10.23919/VLSICircuits52068.2021.9492457","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492457","url":null,"abstract":"A new model for injection-locked dividers leads to a 4.76-mW prototype that operates from 24 GHz to 73 GHz with no need for tuning or adjustments. Occupying an area of 0.037 mm2, the circuit can robustly serve millimeter-wave radios as well as full-rate 28-Gb/s, 56-Gb/s and half-rate 112 Gb/s wireline transceivers.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer OmniDRL:一种具有双模权值压缩和片上稀疏权值转换的29.3 TFLOPS/W深度强化学习处理器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492504
Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, H. Yoo
{"title":"OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer","authors":"Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, H. Yoo","doi":"10.23919/VLSICircuits52068.2021.9492504","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492504","url":null,"abstract":"This paper presents OmniDRL, a 4.18 TFLOPS and 29.3 TFLOPS/W DRL processor. A group-sparse training core and exponent mean delta encoding are proposed to enable weight and feature map compression for every iteration of DRL training. A sparse weight transposer enables on-chip transpose of compressed weight for reducing external memory access. The processor fabricated in 28 nm CMOS technology and occupies 3.6×3.6 mm2 die area. It achieved 7.16 TFLOPS/W energy efficiency for training robot agent (Mujoco Halfcheetah, TD3), which is 2.4× higher than the previous state-of-the-art.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133370708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management SleepRider:一款5.5μW/MHz Cortex-M4 MCU，采用28nm FD-SOI芯片，具有ULP SRAM、生物医学AFE和完全集成的电源、时钟和反向偏置管理
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492365
R. Dekimpe, Maxime Schramme, M. Lefebvre, Adrian Kneip, R. Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, D. Bol
{"title":"SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management","authors":"R. Dekimpe, Maxime Schramme, M. Lefebvre, Adrian Kneip, R. Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, D. Bol","doi":"10.23919/VLSICircuits52068.2021.9492365","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492365","url":null,"abstract":"Ultra-low-power microcontrollers (ULP MCUs) face a performance trade-off between energy-efficient computing during activity periods and low sleep power, associated with limited wake-up time and energy. Adaptive back-biasing in FD-SOI, along with near-threshold operation at ultra-low voltage, has brought significant improvements by dynamically shifting the minimum energy point (MEP) along the frequency axis. This work introduces a highly-integrated 64-MHz ULP Cortex-M4 MCU with 96-kB SRAM in 28nm FD-SOI. A clock and power management unit (CPMU) generates all internal supplies and clocks from a 1.8-V supply, while unified frequency and back-bias regulation (UFBBR) performs PVT compensation. Custom 16-kB ULP SRAMs achieve low read/write access energy, 1.2/0.84pJ/32-bit access respectively, and provide 0.98nW/kB ultra-low-leakage data retention. A low-power biomedical analog front-end enables biopotential monitoring. The MEP is 5.5μW/MHz (8.2μW/MHz including conversion losses). Sleep power is 7.7μW with retention of logic state and 32-kB memory.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130793552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 43nW 32kHz Pulsed Injection TCXO with 4.2ppm Accuracy Using ∆Σ Modulated Load Capacitance 采用∆Σ调制负载电容的43nW 32kHz脉冲注入TCXO，精度为4.2ppm
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492484
Sujin Park, J. Seol, Li Xu, D. Sylvester, D. Blaauw
{"title":"A 43nW 32kHz Pulsed Injection TCXO with 4.2ppm Accuracy Using ∆Σ Modulated Load Capacitance","authors":"Sujin Park, J. Seol, Li Xu, D. Sylvester, D. Blaauw","doi":"10.23919/VLSICircuits52068.2021.9492484","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492484","url":null,"abstract":"This paper presents an ultra-low power temperature-compensated crystal oscillator (TCXO) with a pulsed injection XO driver for IoT applications. Temperature compensation is achieved using a single switched load capacitance, modulated by a ∆ΣM. The ∆ΣM digitizes a piece-wise linear (PWL) approximation of the XO temperature dependence where a coarse 4-bit temperature sensor selects the PWL segment. The proposed 32.768kHz TCXO achieves an accuracy of ±4.2ppm from -20℃ to 85℃ with 3-point trimming and Allan deviation floor of 34 ppb while consuming 43nW.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"465 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133677571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
MePLER: A 20.6-pJ Side-Channel-Aware In-Memory CDT Sampler MePLER:一个20.6 pj侧通道感知的内存CDT采样器
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492498
Dai Li, Yan He, A. Pakala, Kaiyuan Yang
{"title":"MePLER: A 20.6-pJ Side-Channel-Aware In-Memory CDT Sampler","authors":"Dai Li, Yan He, A. Pakala, Kaiyuan Yang","doi":"10.23919/VLSICircuits52068.2021.9492498","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492498","url":null,"abstract":"This work presents a MePLER, an in-Memory cumulative distribution table (CDT) sampler, featuring custom cell derived from NAND-Type CAM for range-matching, pipelined and segmented array for reduced energy, and suppressed timing and power side-channel leakage. The precision and sample range are configurable for different sampling requirements. A 65nm prototype achieves constant 85.9-MSps, 1-sample/cycle throughput, 20.6-pJ/sample efficiency, and 0.03-mm2 footprint.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An 8Ω 5.5W, 0.006% THD+N, 2×VBAT-Swing Switched-Mode Audio Amplifier with Fully-Differential Linear Buck-Boost Topology Achieving Total Efficiency of 87% 一款8Ω 5.5W, 0.006% THD+N, 2×VBAT-Swing全差分线性Buck-Boost拓扑的开关模式音频放大器，总效率为87%
2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492469
Ji-Hun Lee, Hyunsik Kim
{"title":"An 8Ω 5.5W, 0.006% THD+N, 2×VBAT-Swing Switched-Mode Audio Amplifier with Fully-Differential Linear Buck-Boost Topology Achieving Total Efficiency of 87%","authors":"Ji-Hun Lee, Hyunsik Kim","doi":"10.23919/VLSICircuits52068.2021.9492469","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492469","url":null,"abstract":"This paper presents a fully-differential single-inductor linear buck-boost power topology-based switched-mode audio amplifier. The pro-posed buck-boost topology outputs from 0 to 2× battery voltage while improving efficiency by up to 10% compared to the dual-step conversion of Class-D after the step-up. The inductor-freewheeling with a fixed de-energizing phase linearizes the voltage conversion in the buck-boost. The chip fabricated in 0.18-μm achieves 0.006% THD+N and 87% efficiency at a maximum output power of 5.5W on an 8Ω-speaker.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115045946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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