全数字闭环统一保持/唤醒钳在10nm 4核x86 IP

2021 Symposium on VLSI Circuits Pub Date : 2021-06-13 DOI:10.23919/VLSICircuits52068.2021.9492376

C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. Tschanz, M. Khellah

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引用次数: 0

摘要

提出了一种10nm 4核x86 IP，具有多种低功耗状态，包括C1(时钟门控核心)，C6(电源门控核心)和一种称为C1LP的新状态，其中核心电压降低到其保持电压(VRETENTION)。用于C1LP的全数字闭环统一保持钳和用于C6的唤醒显示出33%/28%的核/IP节能，在解决PVT变化影响的同时具有120ns的唤醒延迟。

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All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP

A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (VRETENTION) is presented. All-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33%/28% for core/IP, with 120ns wake up latency while addressing impact of PVT variations.

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来源期刊

2021 Symposium on VLSI Circuits

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