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A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis 基于包络响应分析的射频系统功能表征的BIST解决方案
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.14
Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas
{"title":"A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis","authors":"Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas","doi":"10.1109/ATS.2009.14","DOIUrl":"https://doi.org/10.1109/ATS.2009.14","url":null,"abstract":"This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs 高精度ΣΔ adc的低成本动态测试方法
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.76
Sehun Kook, H. Choi, Vishwanath Natarajan, A. Chatterjee, A. Gomes, Shalabh Goyal, Le Jin
{"title":"Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs","authors":"Sehun Kook, H. Choi, Vishwanath Natarajan, A. Chatterjee, A. Gomes, Shalabh Goyal, Le Jin","doi":"10.1109/ATS.2009.76","DOIUrl":"https://doi.org/10.1109/ATS.2009.76","url":null,"abstract":"In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent over-sampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodology.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder 低开销时复用在线检测:H.264解码器的案例研究
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.24
Ming Gao, K. Cheng
{"title":"Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder","authors":"Ming Gao, K. Cheng","doi":"10.1109/ATS.2009.24","DOIUrl":"https://doi.org/10.1109/ATS.2009.24","url":null,"abstract":"To cope with increasing in-field failure rates for cost-sensitive electronic products, a low-overhead online checking methodology -- Time-Multiplexed Online Checking (TMOC) -- was proposed and demonstrated in [1]. In this paper, we study the area overhead required for employing TMOC in an embedded Field Programmable Gate Array (eFPGA) core. The overheads caused by the relatively low logic density of eFPGA and the interface routing between a design module and its TMOC checker are examined in detail. In a case study of an H.264 decoder design [2], TMOC is compared to a dedicated duplication-based online checking scheme [3], which typically incurs more than 100% area overhead. Experimental results show that TMOC provides significant chip area overhead reduction for online checkers. A reduction of 68% is achieved when one checker is shared by 62 design partitions, for example. TMOC can also help reduce dynamic power overhead of online checking by increasing the number of partitions, at the cost of increased fault detection latency in some partitions.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Testability Exploration of 3-D RAMs and CAMs 三维ram和cam的可测试性探索
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.59
Yu-Jen Huang, Jin-Fu Li
{"title":"Testability Exploration of 3-D RAMs and CAMs","authors":"Yu-Jen Huang, Jin-Fu Li","doi":"10.1109/ATS.2009.59","DOIUrl":"https://doi.org/10.1109/ATS.2009.59","url":null,"abstract":"Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique 基于数字纠错技术的流水线adc减码线性测试方法的待测电路设计
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.18
Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang
{"title":"Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique","authors":"Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang","doi":"10.1109/ATS.2009.18","DOIUrl":"https://doi.org/10.1109/ATS.2009.18","url":null,"abstract":"In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-for-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127149113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Multi-dimensional Pattern Run-Length Method for Test Data Compression 一种测试数据压缩的多维模式运行长度方法
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.49
Lung-Jen Lee, W. Tseng, Rung-Bin Lin, Chen-Lun Lee
{"title":"A Multi-dimensional Pattern Run-Length Method for Test Data Compression","authors":"Lung-Jen Lee, W. Tseng, Rung-Bin Lin, Chen-Lun Lee","doi":"10.1109/ATS.2009.49","DOIUrl":"https://doi.org/10.1109/ATS.2009.49","url":null,"abstract":"This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS’89 benchmarks.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing 一种用于减少高速扫描测试中发射切换活动的关键区域目标测试集修改方案
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.22
K. Enokimoto, X. Wen, Yuta Yamato, K. Miyase, H. Sone, S. Kajihara, Masao Aso, H. Furukawa
{"title":"CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing","authors":"K. Enokimoto, X. Wen, Yuta Yamato, K. Miyase, H. Sone, S. Kajihara, Masao Aso, H. Furukawa","doi":"10.1109/ATS.2009.22","DOIUrl":"https://doi.org/10.1109/ATS.2009.22","url":null,"abstract":"Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133029037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Analysis of Resistive Bridging Defects in a Synchronizer 同步器阻性桥接缺陷分析
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.13
Hyoung-Kook Kim, W. Jone, Laung-Terng Wang, Shianling Wu
{"title":"Analysis of Resistive Bridging Defects in a Synchronizer","authors":"Hyoung-Kook Kim, W. Jone, Laung-Terng Wang, Shianling Wu","doi":"10.1109/ATS.2009.13","DOIUrl":"https://doi.org/10.1109/ATS.2009.13","url":null,"abstract":"This paper presents fault modeling and analysis for resistive bridging defects in a synchronizer constructed with two D flip-flops. Bridging defects are exhaustively injected into any two nodes of the synchronizer to find all possible faults that might occur in the synchronizer, and HSPICE is used to perform circuit analysis.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic Compaction in SAT-Based ATPG 基于sat的ATPG动态压缩
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.31
A. Czutro, I. Polian, P. Engelke, S. Reddy, B. Becker
{"title":"Dynamic Compaction in SAT-Based ATPG","authors":"A. Czutro, I. Polian, P. Engelke, S. Reddy, B. Becker","doi":"10.1109/ATS.2009.31","DOIUrl":"https://doi.org/10.1109/ATS.2009.31","url":null,"abstract":"SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Compact Test Generation for Small-Delay Defects Using Testable-Path Information 基于测试路径信息的小延迟缺陷压缩测试生成
2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.44
D. Xiang, Boxue Yin, K. Chakrabarty
{"title":"Compact Test Generation for Small-Delay Defects Using Testable-Path Information","authors":"D. Xiang, Boxue Yin, K. Chakrabarty","doi":"10.1109/ATS.2009.44","DOIUrl":"https://doi.org/10.1109/ATS.2009.44","url":null,"abstract":"Testing for small-delay defects requires fault-effect propagation along the longest testable paths. However, the selection of the longest testable paths requires high CPU time and leads to large pattern counts. Dynamic test compaction for small-delay defects has remained largely unexplored thus far. We propose a path-selection scheme to accelerate ATPG based on stored testable critical-path information. A new dynamic test-compaction technique based on structural analysis is also introduced. Simulation results are presented for a set of ISCAS’89 benchmark circuits.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115916263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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