{"title":"New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology","authors":"Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, J. Rau","doi":"10.1109/ATS.2009.48","DOIUrl":"https://doi.org/10.1109/ATS.2009.48","url":null,"abstract":"A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don’t care bits (x) as in test compression, and it is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency","authors":"Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang","doi":"10.1109/ATS.2009.67","DOIUrl":"https://doi.org/10.1109/ATS.2009.67","url":null,"abstract":"On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the number of test sessions required to form all the rings. Previous method on ring generation algorithm uses depth-first-search (DFS) based method to generate long rings that may pass more uncovered edges. However, very few of the long rings can be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this paper, we present several techniques to generate rings that can be tested concurrently. (1) Two ring generation algorithms are proposed to generate shorter rings that can be applied in parallel to reduce overall test time. (2) Multilevel framework is applied to optimize parallelism. Experimental results show that the proposed ring generation algorithms improve test application time by 2.25X, and with multilevel framework the improvement is 4.13X. All the ring generation algorithms achieve 100% interconnect fault coverage.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121673451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas
{"title":"A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis","authors":"Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas","doi":"10.1109/ATS.2009.14","DOIUrl":"https://doi.org/10.1109/ATS.2009.14","url":null,"abstract":"This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique","authors":"Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang","doi":"10.1109/ATS.2009.18","DOIUrl":"https://doi.org/10.1109/ATS.2009.18","url":null,"abstract":"In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-for-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127149113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testability Exploration of 3-D RAMs and CAMs","authors":"Yu-Jen Huang, Jin-Fu Li","doi":"10.1109/ATS.2009.59","DOIUrl":"https://doi.org/10.1109/ATS.2009.59","url":null,"abstract":"Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lung-Jen Lee, W. Tseng, Rung-Bin Lin, Chen-Lun Lee
{"title":"A Multi-dimensional Pattern Run-Length Method for Test Data Compression","authors":"Lung-Jen Lee, W. Tseng, Rung-Bin Lin, Chen-Lun Lee","doi":"10.1109/ATS.2009.49","DOIUrl":"https://doi.org/10.1109/ATS.2009.49","url":null,"abstract":"This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS’89 benchmarks.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Enokimoto, X. Wen, Yuta Yamato, K. Miyase, H. Sone, S. Kajihara, Masao Aso, H. Furukawa
{"title":"CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing","authors":"K. Enokimoto, X. Wen, Yuta Yamato, K. Miyase, H. Sone, S. Kajihara, Masao Aso, H. Furukawa","doi":"10.1109/ATS.2009.22","DOIUrl":"https://doi.org/10.1109/ATS.2009.22","url":null,"abstract":"Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133029037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyoung-Kook Kim, W. Jone, Laung-Terng Wang, Shianling Wu
{"title":"Analysis of Resistive Bridging Defects in a Synchronizer","authors":"Hyoung-Kook Kim, W. Jone, Laung-Terng Wang, Shianling Wu","doi":"10.1109/ATS.2009.13","DOIUrl":"https://doi.org/10.1109/ATS.2009.13","url":null,"abstract":"This paper presents fault modeling and analysis for resistive bridging defects in a synchronizer constructed with two D flip-flops. Bridging defects are exhaustively injected into any two nodes of the synchronizer to find all possible faults that might occur in the synchronizer, and HSPICE is used to perform circuit analysis.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Czutro, I. Polian, P. Engelke, S. Reddy, B. Becker
{"title":"Dynamic Compaction in SAT-Based ATPG","authors":"A. Czutro, I. Polian, P. Engelke, S. Reddy, B. Becker","doi":"10.1109/ATS.2009.31","DOIUrl":"https://doi.org/10.1109/ATS.2009.31","url":null,"abstract":"SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact Test Generation for Small-Delay Defects Using Testable-Path Information","authors":"D. Xiang, Boxue Yin, K. Chakrabarty","doi":"10.1109/ATS.2009.44","DOIUrl":"https://doi.org/10.1109/ATS.2009.44","url":null,"abstract":"Testing for small-delay defects requires fault-effect propagation along the longest testable paths. However, the selection of the longest testable paths requires high CPU time and leads to large pattern counts. Dynamic test compaction for small-delay defects has remained largely unexplored thus far. We propose a path-selection scheme to accelerate ATPG based on stored testable critical-path information. A new dynamic test-compaction technique based on structural analysis is also introduced. Simulation results are presented for a set of ISCAS’89 benchmark circuits.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115916263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}