2009 Asian Test Symposium最新文献_第6页

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns 基于制造ATPG模式的自适应信号分析扫描链诊断

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.36

Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, F. Kuo, Yuan-Shih Chen

引用次数: 25

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing 利用部分增强扫描提高延迟故障测试的可观察性

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.78

K. Deepak, Robinson Reyna, Virendra Singh, A. Singh

引用次数: 8

Self-Calibrating Embedded RF Down-Conversion Mixers 自校准嵌入式射频下变频混频器

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.77

A. Goyal, M. Swaminathan, A. Chatterjee

引用次数: 16

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency 具有最大并发性的ieee1500兼容互连测试

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.67

Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang

{"title":"IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency","authors":"Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang","doi":"10.1109/ATS.2009.67","DOIUrl":"https://doi.org/10.1109/ATS.2009.67","url":null,"abstract":"On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the number of test sessions required to form all the rings. Previous method on ring generation algorithm uses depth-first-search (DFS) based method to generate long rings that may pass more uncovered edges. However, very few of the long rings can be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this paper, we present several techniques to generate rings that can be tested concurrently. (1) Two ring generation algorithms are proposed to generate shorter rings that can be applied in parallel to reduce overall test time. (2) Multilevel framework is applied to optimize parallelism. Experimental results show that the proposed ring generation algorithms improve test application time by 2.25X, and with multilevel framework the improvement is 4.13X. All the ring generation algorithms achieve 100% interconnect fault coverage.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121673451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Novel Seed Selection Algorithm for Test Time Reduction in BIST 一种新的减少测试时间的种子选择算法

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.10

R. Chakraborty, D. R. Chowdhury

引用次数: 5

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing 片上积分器泄漏表征技术及其在开关电容电路测试中的应用

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.55

Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang

引用次数: 1

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology 利用x填充方法减少位移和捕获功率的新方案

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.48

Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, J. Rau

引用次数: 3

Delay Fault Diagnosis in Sequential Circuits 时序电路中的延迟故障诊断

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.16

Y. Benabboud, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, Olivia Riewer

引用次数: 4

Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time 告别扫描:一种高覆盖率、低测试数据量和低测试应用时间的非扫描架构

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.17

M. Hsiao, Mainak Banga

{"title":"Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time","authors":"M. Hsiao, Mainak Banga","doi":"10.1109/ATS.2009.17","DOIUrl":"https://doi.org/10.1109/ATS.2009.17","url":null,"abstract":"Scan-based DFT is the de-facto industrial practice for testing integrated circuits (ICs). Variations in the scan architecture to improve test metrics have been the primary focus in recent years. In this paper, we propose a new nonscan DFT in which a subset of the circuit flip-flops are made directly loadable from the primary inputs and another subset of flip-flops are made observable at the output via a state compactor. In this architecture, multiple flip-flops may share the same primary input in the loading mode. A load-enable pin is added to distinguish the direct-loading mode from the functional mode. With a modest area overhead, this architecture offers several attractive features, including (1) at-speed testing, which eliminates the need for scan-shifting and would thus capture delay-related defects, (2) low test data volume and test application time, as we no longer need to store all the scan and response data, (3) high coverages, since the low-testability flipflops are made to be loadable and/or observable, and (4) low test power. Experimental results on large ISCAS’89 circuits validate the aforementioned metrics with 10× to 100× reduction in test application time with respect to Illinois Scan.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies 深亚微米下热功耗约束下基于分区的SoC测试调度

2009 Asian Test Symposium Pub Date : 2009-11-23 DOI: 10.1109/ATS.2009.15

Chunhua Yao, K. Saluja, P. Ramanathan

引用次数: 23