An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing

Abstract

This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator offset. Together with existing SC testing techniques, the leakage characterization technique helps better characterize SC circuits; its application to several popular SC circuits is demonstrated.