Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique

Abstract

In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC [1]. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital Design-for-Test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.