6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

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Comparison of periodic and aperiodic task models for cyber-physical-systems 网络物理系统周期与非周期任务模型的比较
A. Thuy
{"title":"Comparison of periodic and aperiodic task models for cyber-physical-systems","authors":"A. Thuy","doi":"10.1109/ReCoSoC.2011.5981542","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981542","url":null,"abstract":"Aperiodic communication and task execution based on events reflect real world behavior. The successfully applied globally asynchronous locally synchronous approach for distributed on-chip level designs gives reason to discuss such an approach on the software level. Problems of periodic design methodologies for timing critical cyber-physical-systems are pessimistic designs and inflexible execution behavior at run-time. These drawbacks are normally accepted to reach the high-level goals of dependability and predictability. In this paper the periodic communication/task model is contrasted to potential benefits and problems when switching to an aperiodic communication and task model for cyber-physical-systems.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126219142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Re2DA: Reliable and reconfigurable dynamic architecture Re2DA:可靠且可重构的动态架构
H. Pham, L. Devaux, S. Pillement
{"title":"Re2DA: Reliable and reconfigurable dynamic architecture","authors":"H. Pham, L. Devaux, S. Pillement","doi":"10.1109/ReCoSoC.2011.5981519","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981519","url":null,"abstract":"Exploiting partial reconfiguration of commercial FPGAs allows the construction of dynamic multi-processor system-on-chip (MPSoC). This solution offers many advantages such as: low development costs and maintains flexibility as well as high computation power. However, FPGAs are susceptible to electronic particles which can toggle configuration bit values and hence change the correct function of the design. Moreover, that could be important in critical applications which require safety and security. Hence using FPGA requires to integrate fault-tolerance schemes into the system. The reliable MPSoC system called Re2DA, presented in this paper, guarantee the system operation by the use of dynamic reconfiguration. Nearly no hardware overhead is required to perform fault-tolerant feature in the system while timing overhead is kept relatively low.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121745529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Invited paper: Design criteria for dependable System-on-Chip architectures 邀请论文:可靠的片上系统架构的设计标准
T. Hollstein, Faizal Arya Samman, A. Jaiswal, Haoyuan Ying, M. Glesner, K. Hofmann
{"title":"Invited paper: Design criteria for dependable System-on-Chip architectures","authors":"T. Hollstein, Faizal Arya Samman, A. Jaiswal, Haoyuan Ying, M. Glesner, K. Hofmann","doi":"10.1109/ReCoSoC.2011.5981518","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981518","url":null,"abstract":"The rapid improvement of semiconductor technologies is the enabling factor for the design of large-scale System-on-Chip (SoC) architectures. At the same time the scale-down of feature sizes in silicon technologies brings up new challenges as parameter variations of the transistor devices, an increased vulnerability for wear-out effects during the lifetime of the device and increased sensitivity for soft-errors. The overall system reliability is therefore an important topic to be addressed in the SoC design process as well as economic considerations related to manufacturing yield and lifetime maintainability. The aim of this contribution is to outline implications for the design process and to illustrate the dependability aspects at the example of SoC communication architectures being implemented as Networks-on-Chip (NoCs).","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129999549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems 用于多核自适应信号处理系统的可重构流处理器核心,具有相互连接的浮点算术单元
Faizal Arya Samman, S. Pongyupinpanich, M. Glesner
{"title":"Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems","authors":"Faizal Arya Samman, S. Pongyupinpanich, M. Glesner","doi":"10.1109/ReCoSoC.2011.5981539","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981539","url":null,"abstract":"A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems 一种适用于基于fpga的可重构系统的可靠动态片上网络
C. Killian, C. Tanougast, A. Dandache, M. Frihi, S. Toumi
{"title":"A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems","authors":"C. Killian, C. Tanougast, A. Dandache, M. Frihi, S. Toumi","doi":"10.1109/RECOSOC.2011.5981508","DOIUrl":"https://doi.org/10.1109/RECOSOC.2011.5981508","url":null,"abstract":"In this paper, we present a new reliable and dynamic NoC-based communication approach called RCuNoC designed for the FPGA-based reconfigurable systems. The originality of the RCu routers are the online capacity to detect data packet errors and localize if the errors come from input ports or inside of the routers while distinguish between temporary and permanently errors. Our reliable router which requires a low-area architecture is based on the centralization of the buffer, routing logic and error detection/correction/localization blocks. We present the basic concept of the RCu switches, its main advantages and with regards to the other main already proposed dynamic NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and FPGA implementation results are also given.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122106793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs 在基于noc的mpsoc的缓存一致性协议中利用多播消息
Tales Marchesan Chaves, E. Carara, F. Moraes
{"title":"Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs","authors":"Tales Marchesan Chaves, E. Carara, F. Moraes","doi":"10.1109/ReCoSoC.2011.5981492","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981492","url":null,"abstract":"MPSoCs are largely used in embedded systems, allowing the design of complex systems within short time-to-market. The shift in the communication infrastructure, from buses to networks-on-chip (NoCs), adds new design challenges. Standard directory-based cache coherence protocols represent a performance bottleneck due to number of transactions in the network, reducing performance and increasing the energy consumption. State-of-the-art works investigate new protocols, at abstract levels (e.g. TLM), to optimize the performance of the memory organization. Differently from previous works, we investigate the benefits NoCs can bring to directory-based cache coherence protocols using RTL modeling. The main functionality NoCs may provide for the protocols is the way messages are sent through the network. Most NoCs support multicast as a set of unicast messages. Such method is not suitable for cache coherence protocols, because transactions as block invalidate and block update are naturally multicast. This work proposes the use of multicast messages to reduce the number of transactions to improve the performance of cache coherence protocols in NoC-based MPSoCs. Results show that performance of some transactions is improved up to 32% when using multicast messages.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"29 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dynamic resource management in modern multicore SoCs by exposing NoC services 通过公开NoC服务实现现代多核soc中的动态资源管理
Antonios Motakis, Georgios Kornaros, M. Coppola
{"title":"Dynamic resource management in modern multicore SoCs by exposing NoC services","authors":"Antonios Motakis, Georgios Kornaros, M. Coppola","doi":"10.1109/ReCoSoC.2011.5981503","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981503","url":null,"abstract":"Emerging multicore chips containing tens or even hundreds of cores require modern interconnect solutions with increased programmability to support dynamic resource management. Modern embedded devices appear that employ recon-figurable architectures or application specific hardware modules, but still runtime QoS optimizations or dynamic power management require more flexibility from the underlying hardware infrastructure and corresponding middleware. This paper demonstrates a methodology to expose NoC services for adaptive management of hardware resources through a software platform based on Spidergon STNoC technology which consists of a low level driver layer and libraries accessible at user level. Thus, the system designer can exploit the runtime programmable services of a Network-on-Chip so as to provide differentiated network services to multiple independent applications. This methodology can easily be extended to any NoC technology. Spidergon STNoC allows to design customized topologies through the iNoC GUI tool, which is extended to generate the appropriate driver for the Linux kernel. Moreover, an integrated C API allows the developer to capture application specific requirements and dynamically adjust QoS settings of the NoC. In this paper we improve the design methodology to facilitate dynamic management of SoC resources with the aid of appropriate driver and library extensions; we present tools that offer extreme flexibility and real examples of software applications that can exploit the NoC configurability, running on both typical Linux and Android environments.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121932259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Towards a power and energy efficient use of partial dynamic reconfiguration 朝着电力和能源高效利用的部分动态重新配置
Robin Bonamy, D. Chillet, O. Sentieys, S. Bilavarn
{"title":"Towards a power and energy efficient use of partial dynamic reconfiguration","authors":"Robin Bonamy, D. Chillet, O. Sentieys, S. Bilavarn","doi":"10.1109/ReCoSoC.2011.5981540","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981540","url":null,"abstract":"Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. These applications increasingly need flexibility to adapt to their environment. Embed a reconfigurable resource in these SoC enables to flexibilize the hardware by sharing silicon area and limiting the cost of the global circuit. Partial reconfiguration is more and more used since it enables to fully exploit the resource but there is few work in the characterization of the energy consumption during reconfiguration. This paper presents the work on modeling energy using partial dynamic reconfiguration with empty tasks to reduce power consumption and an example on an application.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122754669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Extending Java for heterogeneous embedded system description 为异构嵌入式系统描述扩展Java
G. Plumbridge, N. Audsley
{"title":"Extending Java for heterogeneous embedded system description","authors":"G. Plumbridge, N. Audsley","doi":"10.1109/ReCoSoC.2011.5981527","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981527","url":null,"abstract":"This paper introduces Machine Java, a framework of classes for the Java programming language that enable the description of software for systems with heterogeneous processing elements (such as CPUs, microcontrollers and function accelerators). Intended for the behavioural description of embedded systems, Machine Java encapsulates both the data and control aspects of computation into ‘machine’ objects that are appropriate for mapping onto architecturally diverse multiprocessors. System descriptions in Machine Java avoid the need for a separate programming language for each processing element, and makes explicit description of communications between processors unnecessary. Suitability for a wide variety of hardware platforms is enhanced by avoiding dependence on notions of shared memory or shared timing resources.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Approach of an FPGA based adaptive stepper motor control system 基于FPGA的自适应步进电机控制系统的实现
Nadine Dahm, M. Hübner, J. Becker
{"title":"Approach of an FPGA based adaptive stepper motor control system","authors":"Nadine Dahm, M. Hübner, J. Becker","doi":"10.1109/ReCoSoC.2011.5981531","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981531","url":null,"abstract":"Nowadays, control systems for stepper motors are well defined by using microcontrollers. The stepper motors are very good in positioning tasks and measurement tasks. Now there are some FPGA based developments for stepper motor controlling systems because of the complexity of the controlling system. But the new FPGA systems don't use the whole functionality and benefits of the FPGAs like the parallelism of computing tasks or the right structured Hardware-, Software-Co-Design. In this paper we want to show, that there are many possibilities to use the FPGA benefits for the development of stepper motor control systems and we show also an outlook to new developments and systems. Like an adaptive control system, which controls the parameters of the stepper motor and inspects them for aging.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115063870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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