6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献_第5页

Study and modeling of a new configuration of an optical network on chip (ONOC) using FDTD 利用时域有限差分法研究一种新的片上光网络(ONOC)结构并进行建模

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981538

Malèk Channoufi, P. Lecoy, R. Attia, B. Delacressonniere

{"title":"Study and modeling of a new configuration of an optical network on chip (ONOC) using FDTD","authors":"Malèk Channoufi, P. Lecoy, R. Attia, B. Delacressonniere","doi":"10.1109/ReCoSoC.2011.5981538","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981538","url":null,"abstract":"The increasing need to reduce power consumption and interconnection complexity in optical network on chip requires new configurations and strategies to interconnect cores in one chip. In this paper, we study a new configuration for an optical router on chip «ROTAR». In this router, the number of microrings was reduced to 4, allowing 30% reduction of power consumption compared to Huaxi Gu et al [1]. We study waveguide losses at crossing, bends and resonant rings using the numerical method FDTD. Then, we propose an algorithm to perform a global estimation of all type of losses in our optical network on chip, assuming 1mm2 area and use of 8∗8 routers. Using the Fat-H-Tree topology, we can reduce the number of routers interconnecting 64 cores, compared to the configuration proposed by Huaxi Gu et al [1]. We use GaAs as a substrate to facilitate the integration of optoelectrical devices and silicon waveguides (refraction index = 3,5) surrounded by a layer of silica (1,43) to achieve a strong field confinement in the waveguide. The use of such routers in OnoC has several benefits such as a static and simple routing algorithm and more interconnection capacity compared to λ-router [2].","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127201381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Simulations of NoC topologies for generalized hierarchical completely-connected networks 广义层次全连接网络NoC拓扑的仿真

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981530

T. Takabatake

{"title":"Simulations of NoC topologies for generalized hierarchical completely-connected networks","authors":"T. Takabatake","doi":"10.1109/ReCoSoC.2011.5981530","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981530","url":null,"abstract":"The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spidergon, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. In this paper, we present the performances of the topologies about the communication aspects by the simulation based approach. In particular, Generalized Hierarchical Completely-Connected Networks (HCC) as the NoC topology is presented. An experimental study is conducted to compare the HCC with the other topologies. Simulation results show that the HCC has enough performance to be used by the NoC topology.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122139500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

FPGA physical-design automation using Model-Driven Engineering 使用模型驱动工程的FPGA物理设计自动化

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981495

C. Teodorov, Damien Picard, Loïc Lagadec

引用次数: 9

Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures 用于容错的粗粒度可重构架构的运行时数据路径重新映射

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981536

Sven Eisenhardt, Anja Küster, Thomas Schweizer, T. Kuhn, W. Rosenstiel

引用次数: 4

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 特邀论文:多核平台的并行编程和运行时资源管理框架:2PARMA方法

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981522

C. Silvano, W. Fornaciari, S. Crespi-Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. M. Zins, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, Iraklis Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, J. Ansari, P. Mähönen, B. Vanthournout

{"title":"Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach","authors":"C. Silvano, W. Fornaciari, S. Crespi-Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. M. Zins, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, Iraklis Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, J. Ansari, P. Mähönen, B. Vanthournout","doi":"10.1109/ReCoSoC.2011.5981522","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981522","url":null,"abstract":"Real-time applications, hard or soft, are raising the challenge of unpredictability. This is an extremely difficult problem in the context of modern, dynamic, multiprocessor platforms which, while providing potentially high performance, make the task of timing prediction extremely difficult. Also, with the growing software content in embedded systems and the diffusion of highly programmable and re-configurable platforms, software is given an unprecedented degree of control on resource utilization. The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core computing architectures.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Evaluating the feasibility of network coding for NoCs 评估noc网络编码的可行性

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981493

L. Indrusiak

引用次数: 7

Secure extensions of FPGA soft core processors for symmetric key cryptography 对称密钥加密的FPGA软核处理器的安全扩展

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981500

Lubos Gaspar, Viktor Fischer, L. Bossuet, R. Fouquet

{"title":"Secure extensions of FPGA soft core processors for symmetric key cryptography","authors":"Lubos Gaspar, Viktor Fischer, L. Bossuet, R. Fouquet","doi":"10.1109/ReCoSoC.2011.5981500","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981500","url":null,"abstract":"When used in cryptographic applications, general-purpose processors are often completed by a cryptographic accelerator — crypto-coprocessor. Secret keys are usually stored in the internal registers of the processor, and are vulnerable to attacks on protocols, software/firmware or cache memory. The paper presents three ways of extending soft general purpose processors for cryptographic applications. The proposed extension is aimed at symmetric key cryptography and it guarantees secure key management. Three security zones are created and physically separated in each of three configurations: processor, cipher and key storage zones. In the three zones, the secret keys are manipulated in a different manner — in clear or enciphered, as common data or keys. The security zones are separated on the protocol, system, architectural and physical levels. The proposed principle is validated on Altera NIOS II, Xilinx MicroBlaze and Actel Cortex M1 soft core processor extensions. The NIOS II processor needs fewer clock cycles per data block encryption, because the security module is included in the processor's data path. The data path of the MicroBlaze is unchanged and thus shorter, but additional clock cycles are necessary for data transfers between the processor and the security module. The Cortex M1 processor is connected via AHB bus and the cryptographic extension is accessed as an ordinary peripheral — a coprocessor. Although the interfacing is different, the three processors with their extensions attain the required high security level.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels 混合抽象层次上可重构SoC的功率和性能评估方法

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981516

M. Kühnle, A. Brito, Christoph Roth, Matthias Krüsselin, J. Becker

引用次数: 1

The Xilinx Design Language (XDL): Tutorial and use cases Xilinx设计语言(XDL):教程和用例

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981545

Christian Beckhoff, Dirk Koch, J. Tørresen

引用次数: 86

Evaluation of speculative execution techniques for high-level language to hardware compilation 对高级语言到硬件编译的推测执行技术的评估

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981506

Benjamin Thielmann, Jens Huthmann, Andreas Koch

引用次数: 11