6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献_第6页

Monitoring communication channels on a shared memory multi-processor system on chip 在片上共享存储器多处理器系统上监视通信信道

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981502

Daniela Genius, Nicolas Pouillon

{"title":"Monitoring communication channels on a shared memory multi-processor system on chip","authors":"Daniela Genius, Nicolas Pouillon","doi":"10.1109/ReCoSoC.2011.5981502","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981502","url":null,"abstract":"To meet performance requirements, streaming applications have been mapped to Multi-Processor System on Chip (MPSoC). The Kahn Process Network (KPN) paradigm is sufficient when dealing with pipeline parallelism, but such point-to-point channels are impractical in the presence of massive task farm parallelism. Multi Writer Multi Reader (MWMR) channels generalize KPN in such a way that multiple writers and multiple readers access the same channel. They are implemented as software channels stored in on-chip memory to accommodate access by hardware and software tasks alike. The price to pay for this implementation is increased traffic to and from memory. Typical representatives are telecommunication applications which may treat hundreds or thousands of flows at a time, where the same chain of treatments is applied to every packet. The latency for this treatment depends on the packet's content, and can thus not be foreseen. Among multiple tasks which access a MWMR channel, the time to obtain a lock is variable. In consequence, fill states of MWMR channels vary heavily and it is crucial to monitor it in order to detect potential bottlenecks. We show how this can be done early in the design process by using SoCLib/DSX.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121416341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Self-reparable system on FPGA for single event upset recovery 基于FPGA的单事件故障恢复自修复系统

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981512

Uros Legat, Anton Biasizzo, F. Novak

引用次数: 7

Fast prototyping environment for embedded reconfigurable units 嵌入式可重构单元的快速原型环境

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981496

Damien Picard, Loïc Lagadec

引用次数: 2

Automatic saboteur placement for emulation-based multi-bit fault injection 基于仿真的多比特故障注入的破坏者自动定位

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981521

J. Grinschgl, Armin Krieg, C. Steger, R. Weiss, H. Bock, J. Haid

{"title":"Automatic saboteur placement for emulation-based multi-bit fault injection","authors":"J. Grinschgl, Armin Krieg, C. Steger, R. Weiss, H. Bock, J. Haid","doi":"10.1109/ReCoSoC.2011.5981521","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981521","url":null,"abstract":"During recent years the dependability and security requirements of system-on-chip (SoC) designs have increased tremendously. Both, dependability and security, domains are concerned with operational faults of a random or intentional nature. In former case random faults e.g. caused by radiation or degradation effects could lead to execution errors with possible dramatic results. The security domain is more concerned with intentional faults injected by an adversary during a physical attack to drive the system into an unintended state. The resistance of such a design against faults can be emulated during early design phases using fault injection methods. For these methods the design-under-test is augmented with additional circuitry to emulate faults at predestined locations. One method uses saboteurs, elements that are transparent during normal operation and faulty if activated, are placed into the target system. If this placement process includes a high number of saboteurs, the hardware description manipulation could be a challenge for the design engineer. Therefore this paper presents an automatic placement methodology for fault injection evaluations using saboteur techniques. The automatized process allows for the efficient placement of large amounts of saboteurs. This enables the designer to evaluate a high number of different dependability and fault attack scenarios during early design phases using FPGA-based functional emulation. Selected case studies show how this approach can be applied to a common general purpose architecture in an efficient way.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129017779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21