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6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

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Secure remote reconfiguration of an FPGA-based embedded system 基于fpga的嵌入式系统安全远程重构
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/RECOSOC.2011.5981501
An Braeken, Jan Genoe, S. Kubera, N. Mentens, A. Touhafi, I. Verbauwhede, Y. Verbelen, Jo Vliegen, K. Wouters
{"title":"Secure remote reconfiguration of an FPGA-based embedded system","authors":"An Braeken, Jan Genoe, S. Kubera, N. Mentens, A. Touhafi, I. Verbauwhede, Y. Verbelen, Jo Vliegen, K. Wouters","doi":"10.1109/RECOSOC.2011.5981501","DOIUrl":"https://doi.org/10.1109/RECOSOC.2011.5981501","url":null,"abstract":"This paper describes the protocol, architecture, and implementation details of an FPGA-based embedded system that is able to remotely reconfigure the FPGA, using a TCP/IP connection, in a secure way. When considering the security aspects, we imply data confidentiality, explicit key authentication and data origin authentication. Since these aspects are overhead for the main application, the system is to be as small as possible. Therefore we have focused on compactness rather than on speed for the implementation. The implemented solution exists out of 2 components: a communication part and a cryptographic part. The system can be easily integrated at any point in the design of an FPGA-based embedded system, due to the simple and modular architecture.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123074997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A new mechanism to reduce congestion on TDM networks-on-chips 一种新的机制来减少片上时分复用网络的拥塞
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981515
Daniel Vergeylen, A. K. Lusala, J. Legat
{"title":"A new mechanism to reduce congestion on TDM networks-on-chips","authors":"Daniel Vergeylen, A. K. Lusala, J. Legat","doi":"10.1109/ReCoSoC.2011.5981515","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981515","url":null,"abstract":"This paper presents a mechanism to decrease the congestion on TDM networks handling both Best Effort and Guaranteed Throughput traffic. The mechanism consists of an algorithm which gives an optimal Time Slot to begin transactions between source and destination, thus maximising the probability of successfully reserving a path through the network, to guarantee Quality of Service for the streaming traffic. In order to evaluate the improvements given by the algorithm, a 4×4 2D mesh was simulated in the Soclib environment under random traffic and compared to a same mesh not using the algorithm. Simulation results show that the rate of acceptance of connections from a source to a destination through the network is significantly higher when using the algorithm illustrating a decrease in the global congestion.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129502679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation, integration, and verification of MIMAX WLAN modem MIMAX WLAN调制解调器的实现、集成和验证
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981523
Z. Stamenkovic, K. Tittelbach-Helmrich, M. Wickert, J. Ibáñez, S. Ruiz, George Dimosthenous
{"title":"Implementation, integration, and verification of MIMAX WLAN modem","authors":"Z. Stamenkovic, K. Tittelbach-Helmrich, M. Wickert, J. Ibáñez, S. Ruiz, George Dimosthenous","doi":"10.1109/ReCoSoC.2011.5981523","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981523","url":null,"abstract":"This paper describes the concept, implementation, integration, and verification of an RF-MIMO wireless LAN system called MIMAX. A test setup for trying out the complete MIMAX modem in laptop form factor is presented. The purpose is to verify, debug, and improve all the components and entire system taking into account real-time operation parameters (traffic load, timing, error recovery, etc.). The correctness of the front-end specific MIMAX control functions like beamforming weights handling and setting has been verified. The compatibility with the standard SISO IEEE802.11a WLAN has also been proved.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Genetic mapping of hard real-time applications onto NoC-based MPSoCs — A first approach 硬实时应用在基于noc的mpsoc上的遗传映射-第一种方法
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981532
Paris-alexandros Mesidis, L. Indrusiak
{"title":"Genetic mapping of hard real-time applications onto NoC-based MPSoCs — A first approach","authors":"Paris-alexandros Mesidis, L. Indrusiak","doi":"10.1109/ReCoSoC.2011.5981532","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981532","url":null,"abstract":"Despite its significance to embedded systems industry and research communities, little research has been done on providing guarantees for hard real-time applications running over multicore processors based on wormhole Networks-on-Chip (NoCs). This work takes advantage of recent work on schedulability analysis that is tailored to such platforms, and uses it as a ranking function in a genetic algorithm that is able to evolve task mappings which allow all tasks and communication flows to meet their deadlines in all possible scenarios.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128987802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs HeMPS-S:一种基于noc的均匀mpsoc框架，以fpga为原型
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981498
E. Wächter, Adelcio Biazi, F. Moraes
{"title":"HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs","authors":"E. Wächter, Adelcio Biazi, F. Moraes","doi":"10.1109/ReCoSoC.2011.5981498","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981498","url":null,"abstract":"Current chip transistor density enables the design of multiprocessor systems-on-chip (MPSoCs). MPSoCs are an alternative to create complex computational systems because they reduce the cost, area, power dissipation and design time per chip. Due to their complexity and huge design space to explore for such systems, CAD tools and frameworks to customize MPSoCs are mandatory. The main goal of this paper is to present an open source platform for MPSoC development, named HeMPS Station (HeMPS-S). HeMPS-S is derived from the MPSoC HeMPS. HeMPS-S, in its present state, includes the platform (NoC, processors, DMA, NI), embedded software (microkernel and applications) and a dedicated CAD tool to generate the required binaries and perform debugging. Experiments show the execution of a real application running in HeMPS-S.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121002029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A reconfigurable fabric supporting full C/C++ input 支持全C/ c++输入的可重构结构
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981507
Alexandre A. Junqueira, M. B. Rutzig, F. Itturriet, João Victor Portal, L. Carro
{"title":"A reconfigurable fabric supporting full C/C++ input","authors":"Alexandre A. Junqueira, M. B. Rutzig, F. Itturriet, João Victor Portal, L. Carro","doi":"10.1109/ReCoSoC.2011.5981507","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981507","url":null,"abstract":"Reconfigurable architectures have been widespread used to improve the performance of embedded applications. As most applications of this domain (e.g. video and audio standards) are traditionally specified in high-level programming languages (e.g. C/C++, Java, etc), their optimization process through a hardware accelerator relies on a source code translation from high- to low- level programming languages (e.g. VHDL and Verilog) to program the reconfigurable fabric. However, there is no automatic process to perform such translation. Moreover, the lower the level of the programming language is, the harder it is to manually specify the algorithm, which can greatly affect the hard time-to market imposed by the embedded market. In this paper, we present an easy-programmed reconfigurable fabric that accelerates embedded applications in a total transparent fashion. We propose the use of a run-time binary translation hardware that translates C/C++ source code to the reconfigurable fabric code, without human intervention. Experimental results show great speedups w.r.t. a general-purpose processor and advantageous tradeoff between performance and software productivity w.r.t. a traditional FPGA.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130368880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach 通过携带证明代码的方法实现芯片上可重构系统的硬件安全
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981499
Stephanie Drzevitzky, M. Platzner
{"title":"Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach","authors":"Stephanie Drzevitzky, M. Platzner","doi":"10.1109/ReCoSoC.2011.5981499","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981499","url":null,"abstract":"Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Exploration of MPSoC monitoring and management systems MPSoC监控与管理系统的探索
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981544
Mohammad Fattah, M. Daneshtalab, P. Liljeberg, J. Plosila
{"title":"Exploration of MPSoC monitoring and management systems","authors":"Mohammad Fattah, M. Daneshtalab, P. Liljeberg, J. Plosila","doi":"10.1109/ReCoSoC.2011.5981544","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981544","url":null,"abstract":"A well suited monitoring and management system is becoming a necessity as the number of cores on single chip systems is increasing. Some works have proposed monitoring systems in order to enable off-chip system debugging, while some others have introduced a monitoring approach towards system self-awareness. The latter tries to facilitate self-management of NoC-based MPSoCs in different aspects, such as power, performance, fault tolerance, reconfigurability etc. In this paper, we discuss different solutions and present a qualitative comparison between them. Hierarchical agent-based management systems are also surveyed as a promising solution to cope with different fine and coarse grained demands of a real time network based many-core architectures.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Dataflow programming model for reconfigurable computing 可重构计算的数据流编程模型
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981505
L. Gantel, Amel Khiar, Benoît Miramond, M. A. Benkhelifa, F. Lemonnier, L. Kessal
{"title":"Dataflow programming model for reconfigurable computing","authors":"L. Gantel, Amel Khiar, Benoît Miramond, M. A. Benkhelifa, F. Lemonnier, L. Kessal","doi":"10.1109/ReCoSoC.2011.5981505","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981505","url":null,"abstract":"This paper addresses the problem of image processing algorithms implementation onto dynamically and reconfigurable architectures. Today, these Systems-on-Chip (SoC), offer the possibility to implement several heterogeneous processing elements in a single chip. It means several processors, few hardware accelerators as well as communication mediums between all these components. Applications for this kind of platform are described with software threads, running on processors, and specific hardware accelerators, running on hardware partitions. This paper focuses on the complex problem of communication management between software and hardware actors for dataflow oriented processing, and proposes solutions to leverage this issue.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130069503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Multi-objective mapping for matrix-based nanocomputer architectures 基于矩阵的纳米计算机体系结构多目标映射
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981504
N. Yakymets, S. L. Beux, K. Jabeur, I. O’Connor
{"title":"Multi-objective mapping for matrix-based nanocomputer architectures","authors":"N. Yakymets, S. L. Beux, K. Jabeur, I. O’Connor","doi":"10.1109/ReCoSoC.2011.5981504","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981504","url":null,"abstract":"In this paper, we propose a method for the multi-objective mapping of applications onto matrix-based nanocomputer architectures. These architectures are composed from reconfigurable logic cells interconnected according to a given topology. The power consumption and data propagation delay of each cell depend on its internal function, e.g. NAND, OR, etc. By taking into account these cell characteristics, the mapping method optimizes power consumption, critical path delay and area of the whole system. We experimentally prove that the proposed method is efficient for generating mapping solutions with good trade-off between the optimized metrics. Furthermore, the method allows the comparison of matrix size and interconnect topologies in nanocomputer architectures, and thus aims to facilitate the development of such architectures. Experimental results demonstrate 38% of power reduction for systolic array and 44% of critical path delay improvement for the “Cell Matrix”.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121103325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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