6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

筛选
英文 中文
Notice of Violation of IEEE Publication PrinciplesThe co-simulation interface SystemC/Matlab applied in JPEG algorithm 违反IEEE发布原则的通知JPEG算法采用SystemC/Matlab联合仿真接口
W. Hassairi, M. Bousselmi, M. Abid
{"title":"Notice of Violation of IEEE Publication PrinciplesThe co-simulation interface SystemC/Matlab applied in JPEG algorithm","authors":"W. Hassairi, M. Bousselmi, M. Abid","doi":"10.1109/ReCoSoC.2011.5981535","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981535","url":null,"abstract":"Functional verification is a major part of today's system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink. However, different approaches are a barrier to a unified verification flow. In this paper, we propose a co-simulation interface between SystemC and MATLAB and Simulink to enable functional verification of multi-abstraction levels designs. The resulting verification flow is tested on JPEG compression algorithm. The required synchronization of both simulation environments, as well as data type conversion is solved using the proposed co-simulation flow. We divided into two encoder jpeg parts. First implemented in SystemC which is the DCT is representing the party HW. The second consisting of quantization and entropy encoding is implemented in Matlab is the SW part. For communication and synchronization between these two parts we use S-Function and engine in Simulink matlab. With this research premise, this study introduces a new implementation of a Hardware SystemC of DCT. We compare the result of our simulation compared to SW / SW. We observe a reduction in simulation time you have 88.15%.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Enhancing learning of digital systems using a remote FPGA lab 利用远程FPGA实验室加强数字系统的学习
F. Morgan, Seamus Cawley
{"title":"Enhancing learning of digital systems using a remote FPGA lab","authors":"F. Morgan, Seamus Cawley","doi":"10.1109/ReCoSoC.2011.5981525","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981525","url":null,"abstract":"Learning in digital systems design and reconfigurable computing can be enhanced through applying a learn-by-doing approach on practical hardware systems. This paper presents the web-based RemoteFPGA lab which enables users to interact with a range of demonstrator digital hardware systems, operating in real time on an FPGA. The RemoteFPGA lab provides interactive control of system inputs, and monitoring of signals at any level of the design hierarchy. Users can also integrate their own HDL design descriptions within a RemoteFPGA HDL-based project template, for synthesis and implementation on the RemoteFPGA. Users can create a system block diagram for upload to the RemoteFPGA server. Interactive control and monitor signal icons can be overlayed on the block diagram to provide real-time demonstrations of the user designs. The RemoteFPGA lab provides enhanced visualisation and interaction with FPGA hardware compared to other reported remote FPGA laboratory systems. The paper describes the RemoteFPGA lab elements and demonstrates its use to support learning using two application case studies for illustration.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A SDM-TDM based circuit-switched router for on-chip networks 一种基于SDM-TDM的片上网络电路交换路由器
A. K. Lusala, J. Legat
{"title":"A SDM-TDM based circuit-switched router for on-chip networks","authors":"A. K. Lusala, J. Legat","doi":"10.1145/2362374.2362379","DOIUrl":"https://doi.org/10.1145/2362374.2362379","url":null,"abstract":"This paper proposes a circuit-switched router which combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service “QoS” is easily guaranteed. The proposed router was synthesized on an FPGA and results show that a practicable network-on-chip “NoC” can be built with the proposed router architecture. Simulation results show an increase of the probability of establishing paths through the network.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs 基于低成本spartan-6 fpga的通用图像处理系统自重构平台
S. Bayar, Mehmet Tükel, A. Yurdakul
{"title":"A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs","authors":"S. Bayar, Mehmet Tükel, A. Yurdakul","doi":"10.1109/ReCoSoC.2011.5981513","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981513","url":null,"abstract":"There is still no partial reconfiguration tool support on low-cost Field Programmable Gate Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA families by Xilinx. This forces the designers and engineers, who are using the partial reconfiguration capability of FPGAs, to use expensive families such as Virtex-4, Virtex-5 and Virtex-6 which are officially supported by partial reconfiguration (PR) software. Moreover, Xilinx still does not offer a portable, dedicated self-reconfiguration engine for all of the FPGAs. Self-reconfiguration is achieved with general-purpose processors such as MicroBlaze and PowerPC which are too overqualified for this purpose. In this study, we propose a new self-reconfiguration mechanism for Spartan-6 FPGAs. This mechanism can be used to implement large and complex designs on small FPGAs as chip area can be dramatically reduced by exploiting the dynamic partial reconfiguration feature for on-demand functionality loading and maximal utilization of the hardware. This approach is highly attractive for designing low-cost compute-intensive applications such as high performance image processing systems. For Spartan-6 FPGAs, we have developed hard-macros and exploited the self-reconfiguration engine, compressed Parallel Configuration Access Port (cPCAP) [1], that we designed for Spartan-3. The modified cPCAP core with block RAM controller, bitstream decompressor unit and Internal Configuration Access Port (ICAP) Finite State Machine (FSM) occupies only about 82 of 6,822 slices (1.2% of whole device) on a Spartan-XC6SLX45 FPGA and it achieves the maximum theoretical reconfiguration speed of 200MB/s (ICAP, 16-bit at 100MHz) proposed by Xilinx. We have also implemented a Reconfigurable Processing Element (RPE) whose arithmetic unit can be reconfigured on-the-fly. Multiple RPEs can be utilized to design a General Purpose Image Processing System (GPIPS) that can implement a number of different algorithms during runtime. As an illustrative example, we programmed the GPIPS on Spartan-6 for switching between two applications on-demand such as two-dimensional filtering and block-matching.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129085822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High-performance on-chip network platform for memory-on-processor architectures 用于内存-处理器架构的高性能片上网络平台
M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen
{"title":"High-performance on-chip network platform for memory-on-processor architectures","authors":"M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/ReCoSoC.2011.5981509","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981509","url":null,"abstract":"Three Dimensional Integrated Circuits (3D ICs) are emerging to improve existing Two Dimensional (2D) designs by providing smaller chip areas, higher performance and lower power consumption. Stacking memory layers on top of a multiprocessor layer (logic layer) is a potential solution to reduce wire delay and increase the bandwidth. To fully employ this capability, an efficient on-chip communication platform is required to be integrated in the logic layer. In this paper, we present an on-chip network platform for the logic layer utilizing an efficient network interface to exploit the potential bandwidth of stacked memory-on-processor architectures. Experimental results demonstrate that the platform equipped with the presented network interface increases the performance considerably.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware — Experiences on teaching and research 特邀论文:在可重构硬件中实现数字数据隐藏算法——教学与研究经验
R. Cumplido, C. F. Uribe, José Juan García-Hernández
{"title":"Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware — Experiences on teaching and research","authors":"R. Cumplido, C. F. Uribe, José Juan García-Hernández","doi":"10.1109/ReCoSoC.2011.5981526","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981526","url":null,"abstract":"Digital data hiding algorithms have recently received attention of the research community as an alternative to fight the piracy problem in the Internet era. Several data hiding applications, such as broadcasting monitoring and live performance watermarking, require a real-time multi-channel behavior, also new applications are constantly pushing the limits of available computing systems. This motivates the research on custom architectures, being reconfigurable logic a good option to implement such processing systems. This paper introduces the field of digital data hiding, including a brief review on hardware based architectures and a discussion of the challenges of implementing custom architectures for this type of applications. Also, the authors' experience in teaching and research on hardware architectures for digital data hiding algorithms at the MSc Program on Computer Science at INAOE is discussed.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114466634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RecoNoC: A reconfigurable network-on-chip 一种可重构的片上网络
Robbe Vancayseele, Brahim Al Farisi, W. Heirman, Karel Bruneel, D. Stroobandt
{"title":"RecoNoC: A reconfigurable network-on-chip","authors":"Robbe Vancayseele, Brahim Al Farisi, W. Heirman, Karel Bruneel, D. Stroobandt","doi":"10.1109/ReCoSoC.2011.5981529","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981529","url":null,"abstract":"This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA, using the TMAP dynamic datafolding toolflow to automatically generate the reconfigurable hardware and the software reconfiguration procedures. The results show that, using dynamic datafolding, the overhead of introducing this shortcut mechanism is limited.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125368433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
FPGA bitstream protection with PUFs, obfuscation, and multi-boot FPGA位流保护puf,混淆,和多引导
Sezer Gören, Ozgur Ozkurt, Abdullah Yildiz, H. F. Ugurdag
{"title":"FPGA bitstream protection with PUFs, obfuscation, and multi-boot","authors":"Sezer Gören, Ozgur Ozkurt, Abdullah Yildiz, H. F. Ugurdag","doi":"10.1109/ReCoSoC.2011.5981541","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981541","url":null,"abstract":"With the combination of PUFs, obfuscation, and multi-boot, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Our particular PUF implementation does not steal valuable FPGA real estate from the actual design with the help of multi-boot. We favor multi-boot over self partial reconfiguration as it is easier to implement.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126526332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Efficient congestion-aware selection method for on-chip networks 片上网络的高效拥塞感知选择方法
M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen
{"title":"Efficient congestion-aware selection method for on-chip networks","authors":"M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/ReCoSoC.2011.5981543","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981543","url":null,"abstract":"The choice of routing algorithm can have a large impact on the performance of on-chip networks. As adaptive routing algorithms may return a set of output channels, a selection method (routing policy) is employed to choose the appropriate output channel from the given set. In this paper, we present a novel on-chip network structure to detect the local and non-local congested areas. Based on the presented structure, an efficient congestion-aware selection method is proposed to choose an output channel that allows a packet to be routed through a less congested area.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"415 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FPGA SDK for nanoscale architectures 用于纳米级架构的FPGA SDK
C. Teodorov, Loïc Lagadec
{"title":"FPGA SDK for nanoscale architectures","authors":"C. Teodorov, Loïc Lagadec","doi":"10.1109/ReCoSoC.2011.5981494","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981494","url":null,"abstract":"As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies. From the tool-flow perspective, this architecture is similar to antifuse configurable architectures hence we propose a FPGA SDK based programming environment that support domain-space exploration.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126252252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信