{"title":"A SDM-TDM based circuit-switched router for on-chip networks","authors":"A. K. Lusala, J. Legat","doi":"10.1145/2362374.2362379","DOIUrl":null,"url":null,"abstract":"This paper proposes a circuit-switched router which combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service “QoS” is easily guaranteed. The proposed router was synthesized on an FPGA and results show that a practicable network-on-chip “NoC” can be built with the proposed router architecture. Simulation results show an increase of the probability of establishing paths through the network.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2362374.2362379","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
This paper proposes a circuit-switched router which combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service “QoS” is easily guaranteed. The proposed router was synthesized on an FPGA and results show that a practicable network-on-chip “NoC” can be built with the proposed router architecture. Simulation results show an increase of the probability of establishing paths through the network.