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6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

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SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications SPARTAN项目:在空间应用的可重构平台上高效实现计算机视觉算法
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981524
K. Siozios, D. Diamantopoulos, I. Kostavelis, Evangelos Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, M. Avilés, Iraklis Anagnostopoulos
{"title":"SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications","authors":"K. Siozios, D. Diamantopoulos, I. Kostavelis, Evangelos Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, M. Avilés, Iraklis Anagnostopoulos","doi":"10.1109/ReCoSoC.2011.5981524","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981524","url":null,"abstract":"Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation for space applications. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129234544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Asymmetric cache coherency: Improving multicore performance for non-uniform workloads 非对称缓存一致性:提高非均匀工作负载的多核性能
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981491
J. Shield, J. Diguet, G. Gogniat
{"title":"Asymmetric cache coherency: Improving multicore performance for non-uniform workloads","authors":"J. Shield, J. Diguet, G. Gogniat","doi":"10.1109/ReCoSoC.2011.5981491","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981491","url":null,"abstract":"Asymmetric coherency is a new concept to support non-uniform workloads in multicore processors. We present the theory behind asymmetric coherency policies and show our design requires no additional hardware over an existing system. Asymmetric coherency is designed to provide better performance for asymmetry in a workload and this is applicable to SoC multicores where the applications often are not evenly spread among the processors. The low cost and complexity makes it a desirable new coherency policy for future work. Our results show up to a 60% reduction in coherency costs for unshared data and up to a 174% improvement in memory access time for shared data.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127624439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A prototyping environment for high performance reconfigurable computing 用于高性能可重构计算的原型环境
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981497
George Afonso, R. B. Atitallah, Alexander Loyer, J. Dekeyser, N. Bélanger, Martial Rubio
{"title":"A prototyping environment for high performance reconfigurable computing","authors":"George Afonso, R. B. Atitallah, Alexander Loyer, J. Dekeyser, N. Bélanger, Martial Rubio","doi":"10.1109/ReCoSoC.2011.5981497","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981497","url":null,"abstract":"In the face of power wall and high performance requirements, designers of hardware architectures are directed more and more towards reconfigurable computing with the usage of heterogeneous CPU/FPGA systems. In such architectures, multi-core processors come with high computation rates while the reconfigurable logic offers high performance per watt and adaptability to the application constraints. However, the design of heterogeneous architectures is facing extremely challenging requirements such as the appropriate programming model, design tools, and the rapid system prototyping. Focusing this issue, we present a prototyping environment for heterogeneous CPU/FPGA systems. Within this environment, we conceived a generic and scalable architecture based on a multi-core processor tightly-connected to FPGA in order to meet performance, power and flexibility goals. Furthermore, front-end interfaces are presented in order to establish communication, data sharing, and synchronisation between the different software and hardware processing units. Finally, we defined a design methodology that eases the development of applications onto heterogeneous systems. Our environment is conceived using standard host machine coupled with a Xilinx Virtex 6 FPGA through the PCI Express standard bus. In the experimental part, we evaluate first the reliability of different CPU/FPGA communication solutions in order to bring real-time capabilities to our system. Secondly, we demonstrate the efficiency of the presented design methodology for heterogeneous systems through the FIR signal processing application.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121458690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling 探索异构的基于noc的mpsoc:从FPGA到高级建模
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/RECOSOC.2011.5981517
Luciano Ost, G. M. Almeida, Marcelo G. Mandelli, E. Wächter, S. Varyani, G. Sassatelli, L. Indrusiak, M. Robert, F. Moraes
{"title":"Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling","authors":"Luciano Ost, G. M. Almeida, Marcelo G. Mandelli, E. Wächter, S. Varyani, G. Sassatelli, L. Indrusiak, M. Robert, F. Moraes","doi":"10.1109/RECOSOC.2011.5981517","DOIUrl":"https://doi.org/10.1109/RECOSOC.2011.5981517","url":null,"abstract":"This paper proposes a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. We propose a solution that uses a unified model-based framework, which is calibrated according to area information obtained from FPGA synthesis. Besides, we present the performance of various applications running on different processors on FPGAs aiming to obtain application efficiency characteristics for calibrating the proposed high-level model. The paper also presents three different scenarios and discusses the reduction in terms of energy consumption as well as the end-to-end communication cost for different applications such as MPEG and ADPCM, among others multimedia benchmarks.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115415835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA 差分对路由平衡WDDL双信号设计在基于集群的Mesh FPGA中
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981528
Emna Amouri, Z. Marrakchi, H. Mehrez
{"title":"Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA","authors":"Emna Amouri, Z. Marrakchi, H. Mehrez","doi":"10.1109/ReCoSoC.2011.5981528","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981528","url":null,"abstract":"Cryptographic devices are vulnerable to Differential Power Attacks (DPA). To resist these attacks, the Wave Dynamic Differential Logic (WDDL) has been proposed. However, the limitation of this technique is that it requires balanced routing of the dual rail interconnect between gates, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of routing balance in Mesh FPGA. First, we perform a dual placement in cluster based Mesh FPGA. Then, we propose a differential routing method which achieves a perfectly balanced routed signals in terms of wire length and switch number.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
NoCmodel: An extensible framework for Network-on-Chips modeling nomodel:用于片上网络建模的可扩展框架
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981534
O. Díaz, A. Astarloa, A. Zuloaga, Jesús Lázaro, J. Jiménez
{"title":"NoCmodel: An extensible framework for Network-on-Chips modeling","authors":"O. Díaz, A. Astarloa, A. Zuloaga, Jesús Lázaro, J. Jiménez","doi":"10.1109/ReCoSoC.2011.5981534","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981534","url":null,"abstract":"Network-on-Chips (NoC) is an emerging concept to address the growing complexity in digital electronics systems. However, current design methodology is based on traditional HDL languages written manually or with the help of code generation tools. In order to deal with NoC design and management we create NoCModel: an extensible framework for NoC modeling based on Python language, with support for simulation and code generation. This paper presents the motivation behind the build and use of this tool, the capabilities currently present in it, an explanation of the core and its add-ons and some results obtained from it.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Temperature-based covert channel in FPGA systems FPGA系统中基于温度的隐蔽通道
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981510
T. Iakymchuk, Maciej Nikodem, Krzysztof Kepa
{"title":"Temperature-based covert channel in FPGA systems","authors":"T. Iakymchuk, Maciej Nikodem, Krzysztof Kepa","doi":"10.1109/ReCoSoC.2011.5981510","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981510","url":null,"abstract":"This paper reports the temperature-based covert communication channel implemented in FPGA system. The channel enables bidirectional transmission and exchange of an arbitrary bit stream between two, electrically separated parts of the FPGA circuit during its normal operation. Transmission to and from the FPGA device is also reported. Transmitter and receiver modules are based on ring-oscillator which utilize 60 and 51 look-up tables respectively. The proof of concept was implemented in the Xilinx Spartan-IIE device and allows for transmission speed of 1/8 bit/s between FPGA and external transceiver. Internal communication is faster and allows to transmit up to 1 bit per second.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Partial reconfiguration in the implementation of autonomous radio receivers for space 空间自主无线电接收机实现中的部分重构
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981511
G. Cardarilli, M. Re, Ilir Shuli, L. Simone
{"title":"Partial reconfiguration in the implementation of autonomous radio receivers for space","authors":"G. Cardarilli, M. Re, Ilir Shuli, L. Simone","doi":"10.1109/ReCoSoC.2011.5981511","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981511","url":null,"abstract":"In space mission there are different scenarios where autonomous radio systems are very useful. In this paper we consider one of such scenarios, related to the communication infrastructure for the planet exploration. The basic idea is to obtain significant advantages in autonomous radio receiver implementation by using FPGA dynamic partial reconfiguration. Implementing the most significant part of the radio, we will show as this techniques can be used and what are the advantages we can obtain. In particular, by using this design methodology system complexity and power consumption is reduced improving the overall system reliability (mainly, in relation to possible SEU induced by ions in the configuration memory).","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128083461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Invited paper: System-wide fault management based on IEEE P1687 IJTAG 邀请论文:基于IEEE P1687 IJTAG的全系统故障管理
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981520
A. Jutman, S. Devadze, I. Aleksejev
{"title":"Invited paper: System-wide fault management based on IEEE P1687 IJTAG","authors":"A. Jutman, S. Devadze, I. Aleksejev","doi":"10.1109/ReCoSoC.2011.5981520","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981520","url":null,"abstract":"Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard allows to create an efficient and regular network for handling fault detection information as well as to manage test and system resources as a system-wide background process during the system operation.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125014345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A study on fine granular fault tolerance methodologies for FPGAs fpga的细粒度容错方法研究
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2011-06-20 DOI: 10.1109/ReCoSoC.2011.5981537
Mahtab Niknahad, O. Sander, J. Becker
{"title":"A study on fine granular fault tolerance methodologies for FPGAs","authors":"Mahtab Niknahad, O. Sander, J. Becker","doi":"10.1109/ReCoSoC.2011.5981537","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2011.5981537","url":null,"abstract":"Single Event Upsets will gain more importance for future nanoscale architectures, which will be more sensitive to such effects. Especially for domains like space applications robust redundany methodologies are needed to make use of these new architectures. In this paper we study fine grain redundancy methodologies which can be used to construct high robust designs. Our basic approach is to localize the fault tolerance structure to a fine grain view. We then show two methodologies which are suitable for FPGAs. The methodologies are similar to Triple Modular Redundancy (TMR) which is a widely used approach for mitigating upsets and failures. However for new device generations simply replicating complete systems in TMR manner may not be sufficient anymore especially in harsh environments, such as space applications. We integrate both approaches into standard FPGA tool flows thereby introducing redundancy automatically without user interaction.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128309545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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