K. Siozios, D. Diamantopoulos, I. Kostavelis, Evangelos Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, M. Avilés, Iraklis Anagnostopoulos
{"title":"SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications","authors":"K. Siozios, D. Diamantopoulos, I. Kostavelis, Evangelos Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, M. Avilés, Iraklis Anagnostopoulos","doi":"10.1109/ReCoSoC.2011.5981524","DOIUrl":null,"url":null,"abstract":"Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation for space applications. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.","PeriodicalId":103130,"journal":{"name":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReCoSoC.2011.5981524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation for space applications. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.