Asymmetric cache coherency: Improving multicore performance for non-uniform workloads

Abstract

Asymmetric coherency is a new concept to support non-uniform workloads in multicore processors. We present the theory behind asymmetric coherency policies and show our design requires no additional hardware over an existing system. Asymmetric coherency is designed to provide better performance for asymmetry in a workload and this is applicable to SoC multicores where the applications often are not evenly spread among the processors. The low cost and complexity makes it a desirable new coherency policy for future work. Our results show up to a 60% reduction in coherency costs for unshared data and up to a 174% improvement in memory access time for shared data.