IEEE Open Journal of the Solid-State Circuits Society最新文献_第8页

Timing-Skew Calibration Techniques in Time-Interleaved ADCs 时间交错adc的时序倾斜校准技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-17 DOI: 10.1109/OJSSCS.2024.3519486

Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun

引用次数: 0

Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator 低压高精度开关电容δ - σ调制器的分析与设计

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-16 DOI: 10.1109/OJSSCS.2024.3517600

Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan

引用次数: 0

Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication 高速无线通信中基于cmos的300 ghz收发器的挑战与创新

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-16 DOI: 10.1109/OJSSCS.2024.3519054

Minoru Fujishima

引用次数: 0

A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C 采用浮动环放大器和增益增强米勒负c的150毫秒/秒全动态sar辅助管道ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-09 DOI: 10.1109/OJSSCS.2024.3513255

Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn

{"title":"A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C","authors":"Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn","doi":"10.1109/OJSSCS.2024.3513255","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3513255","url":null,"abstract":"This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"145-156"},"PeriodicalIF":0.0,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783016","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology −11.6 dbm OMA灵敏度0.55 pj /bit 40gb /s光接收机，采用2端口参数设计方法

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-03 DOI: 10.1109/OJSSCS.2024.3510478

Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu

{"title":"A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology","authors":"Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu","doi":"10.1109/OJSSCS.2024.3510478","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3510478","url":null,"abstract":"This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 A rms, an averaged INRC density of 6.4 pA/\u0000<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>\u0000, consumes 11.4 mW of power, and provides 87-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"328-339"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller 基于单片机微环调制器的多目标热控制器发射机

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-27 DOI: 10.1109/OJSSCS.2024.3507754

Ali Sadr;Anthony Chan Carusone

{"title":"A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller","authors":"Ali Sadr;Anthony Chan Carusone","doi":"10.1109/OJSSCS.2024.3507754","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3507754","url":null,"abstract":"This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing \u0000<inline-formula> <tex-math>$4.7~{V}_{text {pp}}$ </tex-math></inline-formula>\u0000 digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating \u0000<inline-formula> <tex-math>$1.7~text {pJ/b}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$40~text {Gb/s}$ </tex-math></inline-formula>\u0000. With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of \u0000<inline-formula> <tex-math>$540~mu text {W}$ </tex-math></inline-formula>\u0000 (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"340-350"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers 基于adc - dsp均衡器的超高速有线接收机的最新进展

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-26 DOI: 10.1109/OJSSCS.2024.3506692

Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim

{"title":"Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers","authors":"Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim","doi":"10.1109/OJSSCS.2024.3506692","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506692","url":null,"abstract":"High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"290-304"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions AI/ML应用中先进封装技术的高带宽芯片互连：挑战和解决方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-26 DOI: 10.1109/OJSSCS.2024.3506694

Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai

{"title":"High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions","authors":"Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai","doi":"10.1109/OJSSCS.2024.3506694","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506694","url":null,"abstract":"The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"351-364"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors 线缆通道行为驱动的电阻式终端技术综述

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-20 DOI: 10.1109/OJSSCS.2024.3503546

Changjae Moon;Minsoo Choi;Myungguk Lee;Byungsub Kim

{"title":"Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors","authors":"Changjae Moon;Minsoo Choi;Myungguk Lee;Byungsub Kim","doi":"10.1109/OJSSCS.2024.3503546","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3503546","url":null,"abstract":"From the perspective of channel behaviors, we review several design techniques of resistive termination for wireline applications. Termination impedances strongly affect the channel behaviors. Their impacts vary a lot depending on the types of interconnects and the circuits. Therefore, termination impedances must be appropriately designed for the target applications. In this article, first, we explain an intuitive analytical transfer function model of wireline channels. The model allows designers to easily and intuitively understand the impacts of the termination resistances on the channel behaviors. Second, we review various resistive termination techniques for LC-dominant channels and discuss their design tradeoffs. Especially, we theoretically explain the relaxed impedance matching technique, which allows designers to violate impedance matching for design improvements at the cost of a negligible penalty in signal integrity. Third, we review various resistive termination techniques for RC-dominant channels and their design tradeoffs. We especially emphasize and theoretically explain why and how the design tradeoffs by resistive terminations in RC-dominant channels are different from the ones in LC-dominant channels.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"305-317"},"PeriodicalIF":0.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758758","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s 高达112gb /s的单端有线串扰对消接收机设计技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-19 DOI: 10.1109/OJSSCS.2024.3502315

Liping Zhong;Quan Pan

{"title":"Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s","authors":"Liping Zhong;Quan Pan","doi":"10.1109/OJSSCS.2024.3502315","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3502315","url":null,"abstract":"The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <\u0000<inline-formula> <tex-math>$10{^{-}10 }$ </tex-math></inline-formula>\u0000 and <\u0000<inline-formula> <tex-math>$10{^{-}12 }$ </tex-math></inline-formula>\u0000 with a single-ended channel loss of 24 and 25 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"318-327"},"PeriodicalIF":0.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10757331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142870210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0