IEEE Open Journal of the Solid-State Circuits Society最新文献_第6页

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion 连续时间流水线ADC：一种用于宽带数据转换的连续时间ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-11 DOI: 10.1109/OJSSCS.2023.3313579

Hajime Shibata

引用次数: 0

A WiFi and Bluetooth Low-Energy Backscatter Combo Chip With Beam Steering Capabilities 具有光束转向功能的 WiFi 和蓝牙低功耗反向散射组合芯片

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-11 DOI: 10.1109/OJSSCS.2023.3308530

Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier

{"title":"A WiFi and Bluetooth Low-Energy Backscatter Combo Chip With Beam Steering Capabilities","authors":"Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier","doi":"10.1109/OJSSCS.2023.3308530","DOIUrl":"10.1109/OJSSCS.2023.3308530","url":null,"abstract":"This article introduces a dual-mode backscatter integrated circuit that supports both WiFi and Bluetooth low-energy (BLE) transmissions. It enables a multiantenna WiFi mode with reconfigurable beam steering of single-sideband (SSB) quadrature phase shift-keying (QPSK) signals, while also facilitating omnidirectional SSB BLE-to-BLE backscatter communication. To achieve beam steering, two techniques are proposed: 1) a transmission-line-less fully reflective SP4T backscatter switch is employed to minimize power loss and maximize the communication range and 2) a multiantenna array is constructed using the aforementioned SP4T switches together with a baseband phase-shifting technique to reradiate the incident WiFi signal with a controllable angle of direction. The chip implementation is based on a 65-nm CMOS process and operates at a power consumption of \u0000<inline-formula> <tex-math>$5.5 mu text{W}$ </tex-math></inline-formula>\u0000 in standby mode. In backscattering mode, it consumes \u0000<inline-formula> <tex-math>$39 mu text{W}$ </tex-math></inline-formula>\u0000 for the single-antenna approach and \u0000<inline-formula> <tex-math>$88 mu text{W}$ </tex-math></inline-formula>\u0000 for the multiantenna approach. The proposed design achieves a worst-case access point (AP)-to-AP range of 35 and 56 m for the single-antenna and multiantenna approaches, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"239-248"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design Techniques for Energy-Efficient Analog-to-Digital Converters 节能模数转换器的设计技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-08 DOI: 10.1109/OJSSCS.2023.3311418

Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae

引用次数: 1

A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks 基于对称压缩三权神经网络的3.8 μ w 10关键字噪声鲁棒关键字识别处理器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-06 DOI: 10.1109/OJSSCS.2023.3312354

Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai

{"title":"A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks","authors":"Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai","doi":"10.1109/OJSSCS.2023.3312354","DOIUrl":"10.1109/OJSSCS.2023.3312354","url":null,"abstract":"A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of \u0000<inline-formula> <tex-math>$3.8 ~mu text{W}$ </tex-math></inline-formula>\u0000 at 250 kHz and the normalized energy efficiency is \u0000<inline-formula> <tex-math>$2.79times $ </tex-math></inline-formula>\u0000 higher than state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"185-196"},"PeriodicalIF":0.0,"publicationDate":"2023-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10242041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79901424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network 具有内置AM–PM补偿和单变压器输出网络的数字功率放大器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-08-11 DOI: 10.1109/OJSSCS.2023.3304599

Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang

{"title":"A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network","authors":"Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang","doi":"10.1109/OJSSCS.2023.3304599","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3304599","url":null,"abstract":"This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and \u0000<inline-formula> <tex-math>$1.2times /1.4times $ </tex-math></inline-formula>\u0000 power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"134-144"},"PeriodicalIF":0.0,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10214532.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics IEEE固态电路学会开放期刊生物医学电子学专刊

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-07-06 DOI: 10.1109/OJSSCS.2023.3281904

Jerald Yoo

{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics","authors":"Jerald Yoo","doi":"10.1109/OJSSCS.2023.3281904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3281904","url":null,"abstract":"Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"63-64"},"PeriodicalIF":0.0,"publicationDate":"2023-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10174830.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network 基于非对称Doherty输出网络的电流型单相数字变送器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-06-28 DOI: 10.1109/OJSSCS.2023.3290550

Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers

{"title":"A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network","authors":"Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3290550","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290550","url":null,"abstract":"This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power \u0000<inline-formula> <tex-math>$(P_{mathrm{ out}})$ </tex-math></inline-formula>\u0000 and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a \u0000<inline-formula> <tex-math>$1.76times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.93times $ </tex-math></inline-formula>\u0000 improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average \u0000<inline-formula> <tex-math>$P_{mathrm{ out}}$ </tex-math></inline-formula>\u0000 of 14 dBm with an r.m.s. error vector magnitude \u0000<inline-formula> <tex-math>$({mathrm{ EVM}}_{mathrm{ rms}})$ </tex-math></inline-formula>\u0000 of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"103-117"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167796.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s 高达56Gb/s的CMOS有线NRZ接收机的设计技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-06-28 DOI: 10.1109/OJSSCS.2023.3290551

Behzad Razavi

引用次数: 0

IEEE Open Journal of the Solid-State Circuits Society IEEE固态电路学会开放期刊

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-04-12 DOI: 10.1109/OJSSCS.2023.3266540

引用次数: 0

A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices 一种适用于高性能五摄像头移动设备的250mW 5.4G像素/真实感重聚焦处理器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-02-14 DOI: 10.1109/OJSSCS.2023.3244759

Po-Han Chen;Shu-Wen Yang;Chao-Tsung Huang

{"title":"A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices","authors":"Po-Han Chen;Shu-Wen Yang;Chao-Tsung Huang","doi":"10.1109/OJSSCS.2023.3244759","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3244759","url":null,"abstract":"Digital refocusing in multicamera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this article, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/s throughput. The hardware accelerator improves the processing speed by \u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$350times $ </tex-math></inline-formula>\u0000 that of the original refocusing algorithm running on a general-purpose processor. The chip is fabricated with 40-nm CMOS technology and comprises 271 kB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames/s under 250 mW power consumption.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"52-62"},"PeriodicalIF":0.0,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10044201.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0